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    DQS-offset and read-RTT-disable edge control
    11.
    发明授权
    DQS-offset and read-RTT-disable edge control 有权

    公开(公告)号：US10153014B1

    公开(公告)日：2018-12-11

    申请号：US15680006

    申请日：2017-08-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kallol Mazumder

    IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4063 ,  H03K19/003 ,  H03K19/0175 ,  G11C7/22 ,  G11C29/02

    Abstract: Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward or a falling edge in a forward direction. A delay chain delays the appropriate edge of received command the number of shifts in the corresponding direction to generate a shifted edge command signal. Combination circuitry then combines a falling edge command signal with a shifted rising edge command signal to form a transformed command.

    Apparatuses and methods for timing provision of a command to input circuitry
    12.
    发明授权
    Apparatuses and methods for timing provision of a command to input circuitry 有权
    用于向输入电路定时提供命令的装置和方法

    公开(公告)号：US09530473B2

    公开(公告)日：2016-12-27

    申请号：US14285476

    申请日：2014-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/225

    Abstract: An apparatus or method may include provision of a command to a data block. An example apparatus includes a command circuit configured to provide a command signal in an internal clock time domain based at least in part on a memory access command received in an external clock time domain. The example apparatus further includes a command path delay configured to delay the command signal. The example apparatus further includes a data strobe generator circuit configured to receive the command signal and a data strobe signal. A plurality of clock edges of the data strobe signal correspond to received data bits associated with the memory access command. The data strobe generator circuit is configured to control input circuitry to capture the data associated with the memory access command based at least in part on the data strobe signal and the command signal.

    Abstract translation: 装置或方法可以包括向数据块提供命令。 一种示例性装置包括命令电路，其被配置为至少部分地基于在外部时钟时域中接收的存储器访问命令来在内部时钟时域中提供命令信号。 示例设备还包括被配置为延迟命令信号的命令路径延迟。 该示例设备还包括数据选通发生器电路，被配置为接收命令信号和数据选通信号。 数据选通信号的多个时钟边缘对应于与存储器访问命令相关联的接收数据位。 数据选通发生器电路被配置为至少部分地基于数据选通信号和命令信号来控制输入电路以捕获与存储器访问命令相关联的数据。

    APPARATUSES AND METHODS FOR ADDRESS DETECTION
    13.
    发明申请
    APPARATUSES AND METHODS FOR ADDRESS DETECTION 审中-公开
    用于寻址检测的装置和方法

    公开(公告)号：US20150213872A1

    公开(公告)日：2015-07-30

    申请号：US14168749

    申请日：2014-01-30

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder ,  Jason M. Brown ,  Derek R. May ,  Jeffrey E. Koelling ,  Roger D. Norwood

    IPC: G11C11/408 ,  G11C11/406

    Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

    Abstract translation: 本文公开了用于地址检测的装置和方法。 示例性设备包括地址过滤器和地址跟踪电路。 地址过滤器可以被配置为接收第一地址并且确定第一地址是否匹配与地址过滤器相关联的多个地址的地址。 地址跟踪电路可以耦合到地址过滤器并且被配置为响应于第一地址与地址过滤器相关联的多个地址的地址匹配的确定来存储第一地址。 地址跟踪电路还可以被配置为基于与第一地址匹配的第二地址来接收第二地址并改变与第一地址相关联的计数。 地址跟踪电路可以被配置为响应于计数选择性地提供第一地址。

    Methods, apparatuses, and circuits for bimodal disable circuits
    14.
    发明授权
    Methods, apparatuses, and circuits for bimodal disable circuits 有权
    双模禁用电路的方法，装置和电路

    公开(公告)号：US08963604B2

    公开(公告)日：2015-02-24

    申请号：US14246328

    申请日：2014-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Eric Booth ,  Tyler J. Gomm ,  Kallol Mazumder ,  Scott E. Smith ,  John F. Schreck

    IPC: H03K3/00 ,  H03L1/00 ,  G06F1/10 ,  H03K21/38 ,  H03K5/13

    CPC classification number: H03L1/00 ,  G06F1/10 ,  H03K5/132 ,  H03K5/133 ,  H03K21/38

    Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

    Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用

    MEMORY DEVICE CLOCK SWAPPING
    15.
    发明申请
    MEMORY DEVICE CLOCK SWAPPING 有权

    公开(公告)号：US20250138574A1

    公开(公告)日：2025-05-01

    申请号：US19010744

    申请日：2025-01-06

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder ,  Navya Sri Sreeram ,  Scott E. Smith

    IPC: G06F1/08 ,  G06F1/10

    Abstract: An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.

    GHOST COMMAND SUPPRESSION IN A HALF-FREQUENCY MEMORY DEVICE
    16.
    发明公开
    GHOST COMMAND SUPPRESSION IN A HALF-FREQUENCY MEMORY DEVICE 审中-公开

    公开(公告)号：US20230223057A1

    公开(公告)日：2023-07-13

    申请号：US18174545

    申请日：2023-02-24

    Applicant: Micron Technology, Inc.

    Inventor： Navya Sri Sreeram ,  Kallol Mazumder

    IPC: G11C7/10

    CPC classification number: G11C7/1039 ,  G11C7/1009 ,  G11C7/1012 ,  G11C7/1093 ,  G11C7/1066

    Abstract: A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.

    Burst clock control based on partial command decoding in a memory device
    19.
    发明授权
    Burst clock control based on partial command decoding in a memory device 有权

    公开(公告)号：US11211103B1

    公开(公告)日：2021-12-28

    申请号：US16996025

    申请日：2020-08-18

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder ,  Takayuki Miyamoto

    IPC: G11C7/22 ,  G06F13/28 ,  G11C7/10 ,  G06F1/12 ,  G06F1/08

    Abstract: Devices and methods include a command input configured to receive a command for a memory device. Second stage wakeup circuitry configured to receive a portion of the command and output an indication of whether the command is a non-burst command based on the portion. Clock gating circuitry is configured to receive an input clock and a wake signal. The clock gating circuitry is also configured to output an internal clock based at least in part on a pulse of the received wake signal. The clock gating circuitry also is configured to maintain the output of the internal clock for a duration based on the indication with the duration being shorter when the indication indicates that the command is a non-burst command.

    APPARATUSES AND METHODS FOR ADDRESS DETECTION
    20.
    发明申请
    APPARATUSES AND METHODS FOR ADDRESS DETECTION 审中-公开

    公开(公告)号：US20200042423A1

    公开(公告)日：2020-02-06

    申请号：US16600355

    申请日：2019-10-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kallol Mazumder ,  Jason M. Brown ,  Derek R. May ,  Jeffrey E. Koelling ,  Roger D. Norwood

    IPC: G06F11/34 ,  G11C11/408 ,  G11C11/406

    Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus it an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

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