公开(公告)号：US20240290396A1

公开(公告)日：2024-08-29

申请号：US18444448

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Tal Sharifie

IPC: G11C16/30 ,  G06F12/02

CPC classification number: G11C16/30 ,  G06F12/0246

Abstract: Methods, systems, and devices for power management associated with memory and a controller are described. A memory system performs a power management operation that accounts for power usage by any combination of application specific integrated circuits (ASICs) and memory arrays. The power management operation includes multiple logical unit numbers (LUNs) assigned to a single ASIC, which increases a quantity of bits for communicating a power usage. An ASIC included in a memory system may utilize twice as many bits for communicating power usage information when compared to a NAND array. As part of the power management operation, an ASIC may transmit, to a controller, a first set of bits indicating a power usage of the ASIC, a first subset of the set of bits transmitted during a first instance of a token ring and a second subset of the set of bits transmitted during a second instance of the token ring.

公开(公告)号：US20240241673A1

公开(公告)日：2024-07-18

申请号：US18622132

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Luigi Pilolli ,  Biagio Iorio

IPC: G06F3/06 ,  G06F1/04 ,  G06F1/3234

CPC classification number: G06F3/0659 ,  G06F1/04 ,  G06F3/0604 ,  G06F3/0679 ,  G06F1/3275

Abstract: A method includes selecting a particular ready/busy pin (R/B#) among a plurality of R/B# pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B# pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

公开(公告)号：US11928343B2

公开(公告)日：2024-03-12

申请号：US17983177

申请日：2022-11-08

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan Scott Parry ,  Luigi Pilolli

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/60

Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

公开(公告)号：US20240061593A1

公开(公告)日：2024-02-22

申请号：US18234522

申请日：2023-08-16

Applicant: Micron Technology, Inc.

Inventor： Hojung Yun ,  Liang Yu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory device includes memory dies. Each memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication. The operations include monitoring a data burst with respect to the memory array, detecting a current reservation trigger associated with the data burst, in response detecting the current reservation trigger, reserving an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst, detecting a plurality of input/output cycles of the data burst following the preamble period, and in response to detecting the number of input/output cycles, reserving, based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.

公开(公告)号：US20230089479A1

公开(公告)日：2023-03-23

申请号：US17993194

申请日：2022-11-23

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jeremy Wayne Butterfield ,  Jeremy Binfet

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C5/14 ,  G11C5/06 ,  G11C11/409

Abstract: A variety of applications can include multiple memory die packages configured to engage in peak power management (PPM) across the multiple packages of memory dies. A communication line coupled to each memory die in the multiple memory die packages can be used to facilitate the PPM. A global management die can start a communication sequence among the multiple memory die packages to share a current budget across the multiple memory die packages by driving a signal on the communication line. Local management dies can use the received signal having clock pulses driven by the global management die on the communication line to engage in the PPM. To engage in global PPM, each memory die can be structured, to be selected as the global management die or a local management die, with one or more controllers to interface with the multiple memory die packages and to handle current budget limits.

公开(公告)号：US20220350504A1

公开(公告)日：2022-11-03

申请号：US17729207

申请日：2022-04-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Xiaojiang Guo

IPC: G06F3/06

Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

公开(公告)号：US11237612B2

公开(公告)日：2022-02-01

申请号：US16548639

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: G06F1/26 ,  G06F1/32 ,  G11C5/14 ,  G11C11/4074 ,  H01L23/00 ,  G06F1/3225 ,  G06F1/3212 ,  G06F1/3234

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

公开(公告)号：US11216219B2

公开(公告)日：2022-01-04

申请号：US16871366

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  John Paul Aglubat ,  Fulvio Rori

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F1/14

Abstract: A memory management operation is executed on a plurality of memory dies of a memory sub-system. The memory sub-system determines whether a first measured current level corresponding to execution of the memory management operation satisfies a condition pertaining to a threshold peak current level. The memory sub-system determines whether a second measured current level corresponding to execution of the memory management operation satisfies the condition pertaining to the threshold peak current level. Mask data is generated identifying the first measured current level and the second measured current level. A request is received from a host system to execute the memory management operation. The memory sub-system performs, based on the mask data, a peak current management action during execution of the memory management operation.

公开(公告)号：US20240288924A1

公开(公告)日：2024-08-29

申请号：US18443955

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Giuseppe Cariello

IPC: G11C16/30

CPC classification number: G06F1/3225 ,  G06F11/3062

Abstract: Methods, systems, and devices for power arbitration for systems of electronic components are described. A system may include a power source, a signaling conductor coupled with a voltage source, and a set of electronic components. One or more of the electronic components may include respective circuitry coupled with the power source and a respective switching component (e.g., a transistor) coupled with the signaling conductor. In some implementations, an electronic component of the set may be configured to determine an operation of its respective circuitry that is associated with a power consumption from the power source. Based on such a determination, the electronic component may switch its respective switching component in accordance with an identifier associated with the electronic component, and determine whether to perform the operation based on monitoring a signal level of the signaling conductor during the switching.

公开(公告)号：US20240143501A1

公开(公告)日：2024-05-02

申请号：US18494841

申请日：2023-10-26

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Luigi Pilolli ,  Liang Yu ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Biagio Iorio

IPC: G06F12/02 ,  G06F1/28

CPC classification number: G06F12/0246 ,  G06F1/28

Abstract: A memory device includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a memory die and control logic, operatively coupled with the memory die, to perform operations including receiving, during a current auxiliary data communication cycle, a token to enable auxiliary data communication, in response to receiving the token, determining whether to communicate auxiliary data via an auxiliary data channel to at least one other memory die of a plurality of memory dies, and in response to determining to communicate the auxiliary data via the auxiliary data channel to the at least one other memory die, causing the auxiliary data to be communicated to the at least one other memory die.