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公开(公告)号：US10885945B2
公开(公告)日：2021-01-05
申请号：US15688667
申请日：2017-08-28
Applicant: Micron Technology, Inc.
Inventor： Gerald John Barkley , Daniele Vimercati , Pierguido Garofalo
Abstract: A plurality of block configurations may be employed for read while write operations. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.
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公开(公告)号：US11854647B2
公开(公告)日：2023-12-26
申请号：US17388359
申请日：2021-07-29
Applicant: Micron Technology, Inc.
Inventor： Pierguido Garofalo
Abstract: A level shifter receives an input signal in a first power domain and generates a corresponding output signal in a second power domain. The transition time of the output signal may be longer during a low-to-high transition than during a high-to-low transition or vice versa. The level shifter may provide two outputs, wherein one of the two outputs has a shorter transition time during a high-to-low transition and the other output has a shorter transition time during a low-to-high transition. By using an inverter on the second output, two non-inverted outputs are generated with different transition times. A ramp selection circuit is used to select between the first output and the inverted second output. The ramp selection circuit selects the output with the shortest transition time.
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13.发明申请公开(公告)号：US20210391868A1
公开(公告)日：2021-12-16
申请号：US16760750
申请日：2019-10-30
Applicant: Micron Technology, Inc.
Inventor： Pierguido Garofalo
IPC: H03M1/06
Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.
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公开(公告)号：US10560085B2
公开(公告)日：2020-02-11
申请号：US16201657
申请日：2018-11-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Pierguido Garofalo
IPC: H03K17/687 , H03K17/06 , G11C7/06 , G11C7/10 , G11C7/22 , G11C7/08 , G11C11/4091 , H03K19/00
Abstract: Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.
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公开(公告)号：US20190149143A1
公开(公告)日：2019-05-16
申请号：US16201657
申请日：2018-11-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Pierguido Garofalo
IPC: H03K17/06 , G11C7/08 , H03K19/00 , H03K17/687 , G11C11/4091 , G11C7/10
CPC classification number: H03K17/063 , G11C7/08 , G11C7/1063 , G11C11/4091 , G11C2207/2245 , H03K17/6874 , H03K19/0013 , H03K2217/0036 , H03K2217/0054
Abstract: Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.
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Patent Agency Ranking
公开(公告)号：US09893723B1
公开(公告)日：2018-02-13
申请号：US15217449
申请日：2016-07-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Pierguido Garofalo
IPC: H03K17/687 , H03K17/06 , G11C7/06 , G11C7/10 , G11C7/22
CPC classification number: H03K17/063 , G11C7/08 , G11C7/1063 , G11C11/4091 , G11C2207/2245 , H03K17/6874 , H03K19/00 , H03K2217/0036 , H03K2217/0054
Abstract: Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.
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公开(公告)号：US20150200007A1
公开(公告)日：2015-07-16
申请号：US14668812
申请日：2015-03-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Gerald John Barkley , Daniele Vimercati , Pierguido Garofalo
CPC classification number: G11C5/025 , G11C7/1042 , G11C8/12 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C16/08 , G11C16/10 , G11C16/26
Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.
Abstract translation: 本文公开的主题涉及方法和装置，诸如包括这种存储装置的存储装置和系统。 在一个装置示例中，可以采用多个块配置。 块配置可以包括类似掺杂的半导体开关的布置。 块配置可以选择存储器阵列的相应瓦片，相应瓦片的特定存储器单元，并且选择应用于特定存储器单元的存储器操作。 存储器阵列的特定切片内的紧邻相邻的块配置可以基本上镜像，并且在存储器阵列的分离的紧邻相邻切片中的紧密相邻的块配置可以基本相似。 用于基本上镜像的块配置的类似掺杂的半导体开关的类似的掺杂扩散区可以被布置成电共享公共的电位信号值电平。 还公开了其它装置和方法。
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公开(公告)号：US11881253B2
公开(公告)日：2024-01-23
申请号：US17544471
申请日：2021-12-07
Applicant: Micron Technology, Inc.
Inventor： Pierguido Garofalo
IPC: G11C11/4091 , G11C11/4099 , G11C5/06 , G11C11/4096 , G11C11/4074
CPC classification number: G11C11/4091 , G11C5/06 , G11C11/4074 , G11C11/4096 , G11C11/4099
Abstract: The present disclosure includes apparatuses, methods, and systems for using an average reference voltage for sensing memory. An embodiment includes a memory having a plurality of memory cells coupled to a common node driver, where a group of the memory cells are coupled to an access line and each respective memory cell of the group is coupled to a different respective sense line, sense circuitry coupled to the different respective sense lines, and circuitry configured to apply an average reference voltage from the common node driver to the sense circuitry during a sense operation being performed on the group of memory cells coupled to the access line.
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公开(公告)号：US20230178144A1
公开(公告)日：2023-06-08
申请号：US17544471
申请日：2021-12-07
Applicant: Micron Technology, Inc.
Inventor： Pierguido Garofalo
IPC: G11C11/4091 , G11C11/4099 , G11C11/4074 , G11C11/4096 , G11C5/06
CPC classification number: G11C11/4091 , G11C11/4099 , G11C11/4074 , G11C11/4096 , G11C5/06
Abstract: The present disclosure includes apparatuses, methods, and systems for using an average reference voltage for sensing memory. An embodiment includes a memory having a plurality of memory cells coupled to a common node driver, where a group of the memory cells are coupled to an access line and each respective memory cell of the group is coupled to a different respective sense line, sense circuitry coupled to the different respective sense lines, and circuitry configured to apply an average reference voltage from the common node driver to the sense circuitry during a sense operation being performed on the group of memory cells coupled to the access line.
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公开(公告)号：US20230036502A1
公开(公告)日：2023-02-02
申请号：US17388359
申请日：2021-07-29
Applicant: Micron Technology, Inc.
Inventor： Pierguido Garofalo
Abstract: A level shifter receives an input signal in a first power domain and generates a corresponding output signal in a second power domain. The transition time of the output signal may be longer during a low-to-high transition than during a high-to-low transition or vice versa. The level shifter may provide two outputs, wherein one of the two outputs has a shorter transition time during a high-to-low transition and the other output has a shorter transition time during a low-to-high transition. By using an inverter on the second output, two non-inverted outputs are generated with different transition times. A ramp selection circuit is used to select between the first output and the inverted second output. The ramp selection circuit selects the output with the shortest transition time.
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