公开(公告)号：US20240223197A1

公开(公告)日：2024-07-04

申请号：US18601429

申请日：2024-03-11

Applicant: Micron Technology, Inc.

Inventor： Pierguido Garofalo

IPC: H03M1/06

CPC classification number: H03M1/0648

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

公开(公告)号：US11942958B2

公开(公告)日：2024-03-26

申请号：US17846683

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Pierguido Garofalo

IPC: H03M1/06

CPC classification number: H03M1/0648

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

公开(公告)号：US11387836B2

公开(公告)日：2022-07-12

申请号：US16760750

申请日：2019-10-30

Applicant: Micron Technology, Inc.

Inventor： Pierguido Garofalo

IPC: H03M1/06

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

公开(公告)号：US20240170049A1

公开(公告)日：2024-05-23

申请号：US18480207

申请日：2023-10-03

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Michele Maria Venturini

IPC: G11C11/4093 ,  G11C11/4078 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C11/4078 ,  G11C11/4096

Abstract: Systems, methods, and apparatus related to unity buffers in memory devices. In one approach, a memory device includes memory arrays having memory cells. The memory device includes access lines to access the memory cells. The memory device includes unity buffers to drive the access line loads. Each buffer has an output current limiter that limits current flow when driving a voltage on the access lines. By limiting the current, the current limiter provides improved frequency response and operating stability for the buffer without the need for a compensation net.

公开(公告)号：US11942151B2

公开(公告)日：2024-03-26

申请号：US17720957

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/0054

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

公开(公告)号：US10164624B2

公开(公告)日：2018-12-25

申请号：US15857144

申请日：2017-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Pierguido Garofalo

IPC: H03K17/687 ,  H03K17/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C7/08 ,  G11C11/4091

Abstract: Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

公开(公告)号：US20180123577A1

公开(公告)日：2018-05-03

申请号：US15857144

申请日：2017-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Pierguido Garofalo

IPC: H03K17/06 ,  G11C7/22 ,  G11C7/06 ,  G11C7/10

CPC classification number: H03K17/063 ,  G11C7/08 ,  G11C7/1063 ,  G11C11/4091 ,  G11C2207/2245 ,  H03K17/6874 ,  H03K19/0013 ,  H03K2217/0036 ,  H03K2217/0054

Abstract: Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

公开(公告)号：US20170358328A1

公开(公告)日：2017-12-14

申请号：US15688667

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Gerald John Barkley ,  Daniele Vimercati ,  Pierguido Garofalo

IPC: G11C5/02 ,  G11C7/10 ,  G11C16/10 ,  G11C8/12 ,  G11C16/26 ,  G11C16/08 ,  G11C13/00

CPC classification number: G11C5/025 ,  G11C7/1042 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.

公开(公告)号：US20240203490A1

公开(公告)日：2024-06-20

申请号：US18590692

申请日：2024-02-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/0054

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

公开(公告)号：US20230335191A1

公开(公告)日：2023-10-19

申请号：US17720957

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/0054

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.