公开(公告)号：US10719237B2

公开(公告)日：2020-07-21

申请号：US14992979

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： Rajesh Sundaram ,  Derchang Kau ,  Owen W. Jungroth ,  Daniel Chu ,  Raymond W. Zeng ,  Shekoufeh Qawami

IPC: G06F3/06 ,  G11C8/12 ,  G11C7/10 ,  G11C16/08

Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

公开(公告)号：US10152262B2

公开(公告)日：2018-12-11

申请号：US15145628

申请日：2016-05-03

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

公开(公告)号：US20170364135A1

公开(公告)日：2017-12-21

申请号：US15693209

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Rajesh Sundaram ,  William Low ,  Sowmiya Jayachandran

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3206 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/4234 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

公开(公告)号：US20170351637A1

公开(公告)日：2017-12-07

申请号：US15685855

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Doyle Rivers ,  Paul D. Ruby ,  Anand S. Ramalingam ,  Rajesh Sundaram ,  Julie M. Walker

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/14

CPC classification number: G06F13/4247 ,  G06F13/14 ,  G06F13/385

Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

公开(公告)号：US20170322749A1

公开(公告)日：2017-11-09

申请号：US15145628

申请日：2016-05-03

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/00

Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

公开(公告)号：US20150046611A1

公开(公告)日：2015-02-12

申请号：US13961377

申请日：2013-08-07

Applicant: Micron Technology, Inc.

Inventor： Doyle Rivers ,  Paul D. Ruby ,  Ramalingam Anandaraj ,  Rajesh Sundaram ,  Julie M. Walker

IPC: G06F13/14

CPC classification number: G06F13/4247 ,  G06F13/14 ,  G06F13/385

Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

Abstract translation: 描述了芯片选择的几种系统和方法。 在一种这样的方法中，设备维护两个标识符（ID_a和ID_m）。 当设备接收到命令时，它检查ID_a和ID_m相对于第三参考标识符（ID_s）的值。 如果ID_a或ID_m等于ID_s，则设备执行该命令，否则设备将忽略该命令。 通过使用两种不同的识别方法，系统具有选择激活设备的选项，能够以快速方式选择多个设备和单个设备之间进行选择性切换。 在另一种这样的方法中，设备可以具有存储诸如ID_a的标识信息的持久区域。 因此，系统功能可以独立于与系统中所有设备的初始ID_a分配所需的物理或逻辑组件相关联的任何缺陷/边际。

公开(公告)号：US11586367B2

公开(公告)日：2023-02-21

申请号：US17376716

申请日：2021-07-15

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C13/00

Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

公开(公告)号：US20220004329A1

公开(公告)日：2022-01-06

申请号：US17376716

申请日：2021-07-15

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F3/06 ,  G11C13/00

Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

公开(公告)号：US11145369B2

公开(公告)日：2021-10-12

申请号：US16832061

申请日：2020-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F12/08 ,  G11C14/00 ,  G11C13/00 ,  G11C16/10 ,  G11C16/34 ,  G11C7/24 ,  G11C8/18

Abstract: According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.

公开(公告)号：US11068183B2

公开(公告)日：2021-07-20

申请号：US16103697

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C13/00

Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.