公开(公告)号：US11715547B2

公开(公告)日：2023-08-01

申请号：US17946207

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Sead Zildzic ,  Junwyn A. Lacsao ,  Paing Z. Htet

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/50

CPC classification number: G11C29/42 ,  G11C11/4074 ,  G11C11/4085 ,  G11C29/44 ,  G11C29/50004

Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.

公开(公告)号：US12217794B2

公开(公告)日：2025-02-04

申请号：US18425619

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

公开(公告)号：US12105961B2

公开(公告)日：2024-10-01

申请号：US17978890

申请日：2022-11-01

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Sead Zildzic ,  Violante Moschiano ,  James Fitzpatrick

IPC: G06F3/06 ,  G11C16/34 ,  G11C29/52

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/3459 ,  G11C29/52

Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

公开(公告)号：US20240069765A1

公开(公告)日：2024-02-29

申请号：US17894794

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0625 ,  G06F3/0679

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

公开(公告)号：US20230307053A1

公开(公告)日：2023-09-28

申请号：US18119997

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Paing Z. Htet ,  Akira Goda ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Junwyn A. Lacsao ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Violante Moschiano

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/26 ,  G11C16/102 ,  G11C16/0433

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

公开(公告)号：US10936392B2

公开(公告)日：2021-03-02

申请号：US16234256

申请日：2018-12-27

Applicant: Micron Technology, Inc.

Inventor： Jung Sheng Hoei ,  Peter Sean Feeley ,  Sampath K. Ratnam ,  Sead Zildzic ,  Kishore Kumar Muchherla

IPC: G06F11/00 ,  G06F11/07 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

Abstract: A processing device in a memory system receives a memory command indicating a read window size and a first read voltage and identifies a read window for a first data block of the memory component having the read window size and centered at the first read voltage. The processing device determines whether a number of bit flips for the first data block within the read window exceeds an error threshold and, in response to the number of bit flips exceeding the error threshold, refreshes data stored on the first data block of the memory component.

公开(公告)号：US12217799B2

公开(公告)日：2025-02-04

申请号：US18119997

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Paing Z. Htet ,  Akira Goda ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Junwyn A. Lacsao ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Violante Moschiano

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

公开(公告)号：US12170113B2

公开(公告)日：2024-12-17

申请号：US18076488

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Akira Goda ,  Jonathan S. Parry ,  Violante Moschiano

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/28

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

公开(公告)号：US20240402922A1

公开(公告)日：2024-12-05

申请号：US18806444

申请日：2024-08-15

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

IPC: G06F3/06

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

公开(公告)号：US20240170057A1

公开(公告)日：2024-05-23

申请号：US18425619

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5671

Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.