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11.发明公开公开(公告)号：US20240281151A1
公开(公告)日：2024-08-22
申请号：US18651032
申请日：2024-04-30
Applicant: Micron Technology, Inc.
Inventor： William C. Filipiak , Elancheren Durai , Quincy R. Holton , Adam Satar , Brett Hunter , David R. Silwanowicz
IPC: G06F3/06 , G11C7/04 , G11C11/406 , G11C16/34
CPC classification number: G06F3/0619 , G06F3/0659 , G06F3/0679 , G11C7/04 , G11C11/40626 , G11C16/3418
Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.
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12.发明授权公开(公告)号：US12001686B2
公开(公告)日：2024-06-04
申请号：US17865203
申请日：2022-07-14
Applicant: Micron Technology, Inc.
Inventor： William C. Filipiak , Elancheren Durai , Quincy R. Holton , Adam Satar , Brett Hunter , David R. Silwanowicz
IPC: G06F1/00 , G06F3/06 , G11C7/04 , G11C11/406 , G11C16/34
CPC classification number: G06F3/0619 , G06F3/0659 , G06F3/0679 , G11C7/04 , G11C11/40626 , G11C16/3418
Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.
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公开(公告)号：US20220276793A1
公开(公告)日：2022-09-01
申请号：US17745389
申请日：2022-05-16
Applicant: Micron Technology, Inc.
Inventor： Liang Yu , William C. Filipiak
Abstract: A request is received from a host system to execute a portion of a memory management operation associated with a memory cell of a plurality of memory cells of one or more memory devices. A voltage parameter level associated with execution of the portion of the memory management operation is identified. A determination is made that a comparison of the voltage parameter level with a voltage parameter level threshold satisfies a condition. A power management action is performed in response to the condition being satisfied.
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公开(公告)号：US20200211660A1
公开(公告)日：2020-07-02
申请号：US16267488
申请日：2019-02-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC: G11C16/34 , G11C16/26 , G11C5/06 , G11C11/413 , G11C8/08
Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.
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公开(公告)号：US20190354421A1
公开(公告)日：2019-11-21
申请号：US15982653
申请日：2018-05-17
Applicant: Micron Technology, Inc.
Inventor： Kevin R. Brandt , William C. Filipiak , Michael G. McNeeley , Kishore K. Muchherla , Sampath K. Ratnam , Akira Goda , Todd A. Marquart
Abstract: Performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device, determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing, and performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.
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Patent Agency Ranking
公开(公告)号：US09659639B2
公开(公告)日：2017-05-23
申请号：US15244424
申请日：2016-08-23
Applicant: Micron Technology, Inc.
Inventor： William C. Filipiak , Violante Moschiano
CPC classification number: G11C11/5642 , G11C7/1063 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , G11C29/021 , G11C29/028 , G11C29/20 , G11C29/42 , G11C29/50004 , G11C29/56004
Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.
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公开(公告)号：US20150340086A1
公开(公告)日：2015-11-26
申请号：US14285848
申请日：2014-05-23
Applicant: Micron Technology, Inc.
Inventor： William C. Filipiak , Violante Moschiano
IPC: G11C11/56
CPC classification number: G11C11/5642 , G11C7/1063 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , G11C29/021 , G11C29/028 , G11C29/20 , G11C29/42 , G11C29/50004 , G11C29/56004
Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.
Abstract translation: 描述了用于阈值电压分析的装置和方法。 用于阈值电压分析的一种或多种方法包括存储对应于一组存储器单元的预期状态指示符，将第一感测电压施加到所述存储器单元组耦合到的所选择的存取线，感测至少一个存储单元 响应于所述第一感测电压来确定所述至少一个所述存储器单元的放电指示符是否响应于所述第一感测电压的施加而改变，并且确定所述第一感测电压是特定的阈值电压 所述至少一个所述存储单元的程序状态。
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公开(公告)号：US11615838B2
公开(公告)日：2023-03-28
申请号：US17688983
申请日：2022-03-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Changhyun Lee , Akira Goda , William C. Filipiak
Abstract: One embodiment of a memory device includes an array of multiple-level memory cells and a controller. The controller is configured to program the multiple-level memory cells via a multiple-pass programming operation, the multiple-pass programming operation to program lower page data in a first pass and program higher page data in a second pass such that memory cells to be programmed to a higher level are programmed in parallel with memory cells to be programmed to a lower level.
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公开(公告)号：US11309039B2
公开(公告)日：2022-04-19
申请号：US17202398
申请日：2021-03-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC: G11C16/34 , G11C16/26 , G11C8/08 , G11C11/413 , G11C5/06
Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.
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公开(公告)号：US11295809B2
公开(公告)日：2022-04-05
申请号：US17074690
申请日：2020-10-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Changhyun Lee , Akira Goda , William C. Filipiak
Abstract: One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes programming higher page data to the memory cells in a second pass of the multiple-pass programming operation such that higher page data subject to the programmed lower page data is programmed prior to higher page data subject to erase data.
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