公开(公告)号：US20130067118A1

公开(公告)日：2013-03-14

申请号：US13671248

申请日：2012-11-07

Applicant: Mosaid Technologies Incorporated

Inventor： Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM ,  Shuji SUMI

IPC: G06F13/14

CPC classification number: G06F13/4243

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

Abstract translation: 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。 在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。 根据设备类型匹配确定，DT与所生成或接收的ID组合。 组合的DT和ID作为传送到下一个设备的分组。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 参考提供给互连设备的设备类型，依次生成ID。 将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

公开(公告)号：US20140122777A1

公开(公告)日：2014-05-01

申请号：US13836113

申请日：2013-03-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： HakJune OH ,  Jin-Ki KIM ,  Young Goan KIM ,  Hyun Woong LEE

IPC: G06F3/06

CPC classification number: G06F3/0661 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/1694

Abstract: A memory controller of a data storage device which communicates with a host, has channel control modules each being configurable to have at three different pinout assignments for interfacing with two different types of memory devices operating with different memory interface protocols. One pinout assignment corresponds to a memory interface protocol where memory devices can be connected in parallel with each other. Two other pinout assignments correspond respectively to inbound and outbound signals of another memory interface protocol where memory devices are serially connected with each other. In this mode of operation, one channel control module is configured to provide the outbound signals while another channel control module is configured to receive the inbound signals. Each memory port of the channel control modules includes port buffer circuitry configurable for different functional signal assignments. The configuration of each channel control module is selectable by setting predetermined ports or registers.

Abstract translation: 与主机通信的数据存储设备的存储器控​​制器具有通道控制模块，每个通道控制模块可配置为具有三种不同的引脚分配，用于与使用不同存储器接口协议操作的两种不同类型的存储器件进行接口。 一个引脚分配对应于存储器设备可以彼此并联连接的存储器接口协议。 另外两个引脚分配分别对应于另一存储器接口协议的入站和出站信号，其中存储器设备彼此串联连接。 在这种操作模式中，一个信道控制模块被配置为提供出站信号，而另一个信道控制模块被配置为接收入站信号。 信道控制模块的每个存储器端口包括可配置用于不同功能信号分配的端口缓冲器电路。 每个通道控制模块的配置可以通过设置预定的端口或寄存器来选择。

公开(公告)号：US20140082260A1

公开(公告)日：2014-03-20

申请号：US13835968

申请日：2013-03-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： HakJune OH ,  Jin-Ki KIM ,  Young Goan KIM ,  Hyun Woong LEE

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/385

Abstract: A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol. Each memory interface port of the memory controller includes port buffer circuitry configurable for different functional signal assignments, based on the selected memory interface protocol to be used. The interface circuitry configuration for each memory interface port is selectable by setting a predetermined port or registers of the memory controller.

Abstract translation: 与主机进行通信的数据存储设备的存储器控​​制器可配置为具有用于与相应不同类型的存储器件接口的至少两个不同的引脚分配。 每个引脚分配对应于特定的存储器接口协议。 存储器控制器的每个存储器接口端口基于所使用的选择的存储器接口协议，包括可配置用于不同功能信号分配的端口缓冲器电路。 通过设置存储器控制器的预定端口或寄存器来选择每个存储器接口端口的接口电路配置。

公开(公告)号：US20140010022A1

公开(公告)日：2014-01-09

申请号：US14026359

申请日：2013-09-13

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki KIM

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C5/14 ,  G11C5/143 ,  G11C7/20 ,  G11C16/20

Abstract: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Abstract translation: 兼容异步操作和同步串行操作的双功能存储器件架构。 双功能存储设备架构包括具有两个不同功能分配的一组物理端口。 存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。 信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。 模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。 开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。 适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

公开(公告)号：US20130343125A1

公开(公告)日：2013-12-26

申请号：US13799765

申请日：2013-03-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM ,  Jin-Ki KIM

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5641

Abstract: Apparatus and methods for carrying out operations in a non-volatile memory cell having multiple memory states are disclosed. One of the methods is a method for programming N bits in a non-volatile memory cell configured to store up to N+1 bits, where N is an integer greater than zero. The method for programming includes programming N bits of data in the cell. The method for programming also includes programming an additional bit of data that is a logical function of the N bits of data in the cell. The cell is configured to provide 2N+1 threshold voltage ranges for bit storage and, in accordance with the logical function: i) a first set of 2N threshold voltage ranges of the 2N+1 threshold voltage ranges are used to store the N bits of data; and ii) a remaining second set of 2N threshold voltage ranges alternating with the first set are unused.

Abstract translation: 公开了在具有多个存储器状态的非易失性存储单元中进行操作的装置和方法。 其中一种方法是用于在非易失性存储单元中编程N位的方法，该非易失性存储单元被配置为存储多达N + 1位，其中N是大于零的整数。 编程方法包括在单元格中编程N位数据。 用于编程的方法还包括编程作为单元中N位数据的逻辑功能的附加位数据。 电池被配置为提供用于位存储的2N + 1阈值电压范围，并且根据逻辑功能：i）使用2N + 1个阈值电压范围的2N个阈值电压范围的第一组来存储N + 数据; 和ii）与第一组交替的2N个阈值电压范围的剩余的第二组未使用。

公开(公告)号：US20130170298A1

公开(公告)日：2013-07-04

申请号：US13776757

申请日：2013-02-26

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM ,  HakJune OH ,  Hong Beom PYEON ,  Steven PRZYBYLSKI

IPC: G11C16/10

CPC classification number: G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

Abstract translation: 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

公开(公告)号：US20140192593A1

公开(公告)日：2014-07-10

申请号：US14208812

申请日：2014-03-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM

IPC: G11C16/34

CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

Abstract translation: 用于多电平闪存单元的阈值电压分配方案，其中擦除阈值电压和至少一个编程的阈值电压位于擦除电压域中。 在擦除电压域中至少有一个编程的阈值电压降低了Vread电压电平，以最小化读取干扰效应，同时随着编程状态之间的阈值电压距离最大化，延长多电平闪存单元的使用寿命。 编程电压域大于0V时，擦除电压域可以小于0V。 因此，用于程序验证和读取具有在擦除电压域中的编程阈值电压和编程电压域的多电平闪存单元的电路使用负和正高电压。

公开(公告)号：US20140036435A1

公开(公告)日：2014-02-06

申请号：US13800897

申请日：2013-03-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM

IPC: G06F1/20

CPC classification number: G06F1/20 ,  G06F1/203

Abstract: A storage system sized to fit within a standard magnetic hard disk drive (HDD) form factor. The storage system includes a solid state disk (SSD) and a cooling means thermally coupled to the body of the SSD. The components of the SSD occupy a smaller volume of space than magnetic HDD's. In particular, while the SSD has width and length dimensions matching those of the HDD form factor, the SSD has a height dimension that is less than the HDD form factor. Accordingly, the volume of space between the HDD form factor height and the SSD height is beneficially occupied by the cooling means. The storage system can be then be used as a direct replacement for HDD as it can fit within HDD bays configured for the standardized HDD form factor.

Abstract translation: 一种尺寸适合标准磁性硬盘驱动器（HDD）外形尺寸的存储系统。 存储系统包括固态盘（SSD）和热耦合到SSD的主体的冷却装置。 SSD的组件占据比磁性HDD更小的空间。 特别地，虽然SSD的宽度和长度尺寸与HDD外形尺寸相匹配，但SSD的高度尺寸小于HDD外形尺寸。 因此，HDD形状因数高度和SSD高度之间的空间体积被冷却装置有利地占据。 然后可以将存储系统用作HDD的直接替代品，因为它可以适用于为标准化HDD形状因子配置的HDD托架中。

公开(公告)号：US20140022846A1

公开(公告)日：2014-01-23

申请号：US14032816

申请日：2013-09-20

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki KIM

IPC: G11C16/16

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

Abstract: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

Abstract translation: 具有连接到页缓冲器的存储器阵列的多个位线的NAND闪存库，其中连接到相同位线的NAND单元串形成在至少两个阱扇区中。 在擦除操作期间，至少一个阱区可以选择性地耦合到擦除电压，使得未选择的阱区被禁止接收擦除电压。 当井区的面积减小时，每个井区的电容相应减小。 因此，当电荷泵电路驱动能力保持不变时，可以获得NAND闪速存储单元相对于单个存储器组的更高速擦除。 或者，通过将具有特定面积的阱段与具有降低的驱动能力的电荷泵相匹配来获得对应于单阱存储器组的恒定擦除速度。 降低的驱动电容电荷泵将占用较少的半导体芯片面积，从而降低成本。

公开(公告)号：US20140010019A1

公开(公告)日：2014-01-09

申请号：US14022805

申请日：2013-09-10

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki KIM

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G06F12/0246 ,  G06F2212/7204 ,  G06F2212/7206 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.

Abstract translation: 一种用于延长闪存设备的使用寿命的方法和系统。 闪存器件是动态配置的，以每单元单位（SBC）存储模式或每单元多位（MBC）模式存储数据。 在MBC存储模式中，单元可以具有多种可能状态之一，其中每个状态由相应的阈值电压范围定义。 在SBC模式中，单元可以具有与彼此不相邻的MBC存储模式的状态对应的阈值电压的状态，以改善单元的可靠性特性。