公开(公告)号：US20130169343A1

公开(公告)日：2013-07-04

申请号：US13777645

申请日：2013-02-26

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM

IPC: H01L21/82 ,  H03K17/00 ,  H01L21/02

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/06 ,  H01L21/02697 ,  H01L21/82 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/544 ,  H01L24/03 ,  H01L24/16 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/14 ,  H03K17/00 ,  H01L2924/00

Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Abstract translation: 在适用于互连IC堆叠的集成电路（IC）中，除了不间断的TSV之外，还提供了中断的通硅通孔（TSV）。 中断的TSV提供除了堆栈的IC之间的公共并行路径之外的信号路径。 这允许使用TSV实现IC识别方案和其他功能，而不需要堆叠的替代IC的角旋转。

公开(公告)号：US20130343125A1

公开(公告)日：2013-12-26

申请号：US13799765

申请日：2013-03-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM ,  Jin-Ki KIM

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5641

Abstract: Apparatus and methods for carrying out operations in a non-volatile memory cell having multiple memory states are disclosed. One of the methods is a method for programming N bits in a non-volatile memory cell configured to store up to N+1 bits, where N is an integer greater than zero. The method for programming includes programming N bits of data in the cell. The method for programming also includes programming an additional bit of data that is a logical function of the N bits of data in the cell. The cell is configured to provide 2N+1 threshold voltage ranges for bit storage and, in accordance with the logical function: i) a first set of 2N threshold voltage ranges of the 2N+1 threshold voltage ranges are used to store the N bits of data; and ii) a remaining second set of 2N threshold voltage ranges alternating with the first set are unused.

Abstract translation: 公开了在具有多个存储器状态的非易失性存储单元中进行操作的装置和方法。 其中一种方法是用于在非易失性存储单元中编程N位的方法，该非易失性存储单元被配置为存储多达N + 1位，其中N是大于零的整数。 编程方法包括在单元格中编程N位数据。 用于编程的方法还包括编程作为单元中N位数据的逻辑功能的附加位数据。 电池被配置为提供用于位存储的2N + 1阈值电压范围，并且根据逻辑功能：i）使用2N + 1个阈值电压范围的2N个阈值电压范围的第一组来存储N + 数据; 和ii）与第一组交替的2N个阈值电压范围的剩余的第二组未使用。

公开(公告)号：US20130326090A1

公开(公告)日：2013-12-05

申请号：US13903418

申请日：2013-05-28

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM

IPC: G06F11/30 ,  G06F3/06

CPC classification number: G06F11/3065 ,  G06F3/0688 ,  G06F11/3037 ,  G06F11/3055 ,  G06F11/3082 ,  G06F13/1684 ,  G06F13/4256 ,  G11C7/1063

Abstract: A semiconductor device includes a bridging device having an external data interface, an external status interface, and a plurality of internal data interfaces. A plurality of memory devices are each connected to the bridging device via one of the internal data interfaces. Each of the memory devices has a ready/busy output connected to an input of the bridging device. The bridging device is configured to output a current state of each ready/busy output in a packetized format on the external status interface in response to a status request command received on the external status interface; and read information from a status register of a selected memory device over one of the internal data interfaces and provide the information on the external data interface in response to a status read command received on the external data interface. A method of operating a semiconductor device is also disclosed.

Abstract translation: 半导体器件包括具有外部数据接口，外部状态接口和多个内部数据接口的桥接器件。 多个存储器件各自经由内部数据接口之一连接到桥接器件。 每个存储器件具有连接到桥接器件的输入的就绪/忙碌输出。 桥接装置被配置为响应于在外部状态接口上接收的状态请求命令，在外部状态接口上以分组格式输出每个就绪/忙碌输出的当前状态; 并通过一个内部数据接口从所选择的存储器设备的状态寄存器读取信息，并根据在外部数据接口上接收到的状态读取命令提供有关外部数据接口的信息。 还公开了一种操作半导体器件的方法。

公开(公告)号：US20130309810A1

公开(公告)日：2013-11-21

申请号：US13951132

申请日：2013-07-25

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM

IPC: H01L21/82

CPC classification number: H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Abstract translation: 半导体器件具有安装在基板上的多个堆叠的半导体管芯。 每个模具具有相似的尺寸。 每个管芯具有沿着管芯的接合边缘布置的第一多个接合焊盘。 将第一组骰子安装到衬底上，其中接合边缘沿第一方向定向。 将第二组骰子安装到基板上，其中接合边缘沿与第一方向相反的第二方向定向。 每个模具相对于剩余的骰子在第二方向上通过相应的横向偏移距离而在第二方向上侧向偏移，使得每个模具的焊盘不会在垂直于衬底的方向上设置在衬底和剩余骰子的任何部分之间。 多个接合线将接合焊盘连接到衬底。 还公开了半导体器件的制造方法。

公开(公告)号：US20130134607A1

公开(公告)日：2013-05-30

申请号：US13687198

申请日：2012-11-28

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM

IPC: H01L23/52

CPC classification number: H01L23/52 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device is disclosed, comprising a substrate having at least one substrate bonding pad. A plurality of semiconductor dies are stacked on the substrate. Each semiconductor die has at least one die bonding pad located on an active surface of the die. A plurality of interposers are each mounted on a corresponding one of the semiconductor dies. Each interposer has an aperture formed therethrough in alignment with the at least one die bonding pad. An electrical connection between the at least one die bonding pad and the at least one substrate bonding pad is formed at least in part by the interposer. The electrical connection includes at least one wire bond.

Abstract translation: 公开了一种半导体器件，包括具有至少一个衬底接合焊盘的衬底。 多个半导体管芯被堆叠在基板上。 每个半导体管芯具有位于管芯的有效表面上的至少一个管芯接合焊盘。 多个插入件分别安装在相应的一个半导体管芯上。 每个插入器具有与至少一个管芯接合焊盘对准的通孔形成的孔。 所述至少一个管芯接合焊盘和所述至少一个衬底接合焊盘之间的电连接至少部分地由所述插入件形成。 电连接包括至少一个引线接合。