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    MEMORY DEVICE AND OPERATION METHOD
    12.
    发明申请
    MEMORY DEVICE AND OPERATION METHOD 有权
    存储器和操作方法

    公开(公告)号：US20160328288A1

    公开(公告)日：2016-11-10

    申请号：US14703183

    申请日：2015-05-04

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Hsin-Yi Ho ,  Hsiang-Lan Lung ,  Wei-Chih Chien ,  Tu-Shun Chen ,  Chia-Jung Chen

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F3/0683 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

    Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.

    Abstract translation: 提供了一种存储器件及其操作方法，并且存储器件的操作方法包括以下步骤。 执行编程操作以将原始数据写入存储器件中的第一存储器阵列。 验证第一存储器阵列中的原始数据，并根据验证结果确定是否生成写入信号。 根据原始数据生成纠错码，并将纠错码和写入地址临时存储在存储装置的缓冲电路中。 当产生写入信号时，将缓冲电路中的纠错码和写入地址写入存储器件中的第二存储器阵列。

    Managing secure writes in semiconductor devices
    13.
    发明授权
    Managing secure writes in semiconductor devices 有权

    公开(公告)号：US12086457B2

    公开(公告)日：2024-09-10

    申请号：US17881078

    申请日：2022-08-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0622 ,  G06F3/0679

    Abstract: Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

    High performance secure read in secure memory providing a continuous output of encrypted information and specific context
    14.
    发明授权
    High performance secure read in secure memory providing a continuous output of encrypted information and specific context 有权

    公开(公告)号：US11960769B2

    公开(公告)日：2024-04-16

    申请号：US17824226

    申请日：2022-05-25

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0679

    Abstract: A memory device includes a command decoder that implements security logic to detect a command sequence to read a security region of a memory array with continuous encrypted data and to output/input specific contexts for the data. Output/input of specific contexts can be during a dummy cycle to achieve greater performance. A host interfacing can, for example, execute a single command to both get the encrypted data and specific contexts that were used to encrypt the data. Our technology can implement transferring data on the system bus in ciphertext and encrypted by a different Nonce or a different session key than used in a previous transfer operation. In this way, data will be represented with different ciphertext on the bus at different sessions; thereby defending against a replay attack.

    MANAGING SECURE WRITES IN SEMICONDUCTOR DEVICES
    15.
    发明公开
    MANAGING SECURE WRITES IN SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230259301A1

    公开(公告)日：2023-08-17

    申请号：US17881078

    申请日：2022-08-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0622 ,  G06F3/0679

    Abstract: Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

    Memory chip having security verification function and memory device
    16.
    发明授权
    Memory chip having security verification function and memory device 有权

    公开(公告)号：US11520933B2

    公开(公告)日：2022-12-06

    申请号：US16726284

    申请日：2019-12-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F21/72 ,  G06F21/62 ,  G06F12/1009

    Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

    Multi-chip package, controlling method of multi-chip package and security chip
    18.
    发明授权
    Multi-chip package, controlling method of multi-chip package and security chip 有权

    公开(公告)号：US10969991B2

    公开(公告)日：2021-04-06

    申请号：US15998456

    申请日：2018-08-15

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F3/06

    Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.

    Adjustable writing circuit
    19.
    发明授权
    Adjustable writing circuit 有权

    公开(公告)号：US09779810B2

    公开(公告)日：2017-10-03

    申请号：US15052388

    申请日：2016-02-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Chia-Jung Chen ,  Scott C. Lewis

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0038 ,  G11C2013/0092

    Abstract: A write pulse driver is provided. The write pulse driver includes a parameter storage, storing a set of parameters specifying characteristics of a write pulse, and driver circuitry configured to generate the write pulse on an output node, the write pulse having a leading edge, a trailing edge and an intermediate segment between the leading edge and the trailing edge, wherein the driver circuitry includes pulse shaping circuits that set shape characteristics of at least one of an amplitude, a duration and a slope of more than one of the leading edge, the trailing edge and the intermediate segment of the write pulse using the set of parameters.

    Memory device and operation method
    20.
    发明授权
    Memory device and operation method 有权
    存储器和操作方法

    公开(公告)号：US09507663B1

    公开(公告)日：2016-11-29

    申请号：US14703183

    申请日：2015-05-04

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Hsin-Yi Ho ,  Hsiang-Lan Lung ,  Wei-Chih Chien ,  Tu-Shun Chen ,  Chia-Jung Chen

    IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

    CPC classification number: G06F3/0683 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

    Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.

    Abstract translation: 提供了一种存储器件及其操作方法，并且存储器件的操作方法包括以下步骤。 执行编程操作以将原始数据写入存储器件中的第一存储器阵列。 验证第一存储器阵列中的原始数据，并根据验证结果确定是否生成写入信号。 根据原始数据生成纠错码，并将纠错码和写入地址临时存储在存储装置的缓冲电路中。 当产生写入信号时，将缓冲电路中的纠错码和写入地址写入存储器件中的第二存储器阵列。

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