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公开(公告)号：US07365554B2
公开(公告)日：2008-04-29
申请号：US11092885
申请日：2005-03-29
IPC分类号： G01R31/02
CPC分类号： G11C5/143 , G01R19/16552 , G11C11/401 , G11C11/4074 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C2029/5004
摘要： An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.
摘要翻译： 集成电路包括具有用于施加参考电压的第一输入端子的电流发生器电路和用于施加由外部施加的电源电压内部由电压发生器电路产生的输入电压的第二输入端子。 电流发生器电路通过互连连接到输出端子。 在集成电路的测试操作状态下，第一电流在互连上流动。 电流发生器电路在随后的第二测试周期中在测试操作状态的第一测试周期和第二部分电流中产生第一部分电流。 部分电流各自叠加在互连上的第一电流上。 因此，在测试操作状态期间，输出端子发生三个电流。 电流发生器电路的内部产生的输入电压由三个电流和参考电压确定。
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公开(公告)号：US07224627B2
公开(公告)日：2007-05-29
申请号：US11100617
申请日：2005-04-07
IPC分类号： G11C7/00
CPC分类号： G11C29/12005 , G11C29/12
摘要： Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.
摘要翻译： 集成半导体电路，特别是动态随机存取存储器包括用于从外部施加的电源电压产生内部电压电平的多个发生器电路。 在测试期间，内部电压电平由发生器电路输出端产生的输出电压改变为外部施加的测试电压。 如果测试电压超出公差范围，则半导体电路可能被破坏。 与发生器电路并联连接的保护电路限制输出电压。
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公开(公告)号：US20050218960A1
公开(公告)日：2005-10-06
申请号：US11092963
申请日：2005-03-30
CPC分类号： G11C29/1201 , G01R31/275 , G01R31/2884 , G11C29/48 , G11C29/50 , G11C2029/5002
摘要： An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.
摘要翻译： 集成电路包括电路部件，第一控制电路和可切换电阻网络。 输入电压被馈送到输入侧的电路部件。 由第一控制电路产生的控制信号被馈送到电路部件的控制端。 利用可切换电阻网络，第一电阻或第二电阻连接在电路部件的输出端和集成电路的输出端之间，以在电路部件的输入侧和输出端之间产生电压降。 集成电路使得可以以取决于控制信号的方式在电路部件的输出端产生电流以及在电路部件的输入侧和输出端子之间落下的电压。 集成电路的晶体管的特性曲线族由集成电路确定。
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14.发明申请IC Chip Package, Test Equipment and Interface for Performing a Functional Test of a Chip Contained Within Said Chip Package 审中-公开IC芯片封装，用于执行所述芯片封装内包含的芯片的功能测试的测试设备和接口公开(公告)号：US20080079455A1
公开(公告)日：2008-04-03
申请号：US11866677
申请日：2007-10-03
申请人： Joerg Vollrath , Marcin Gnat , Ralf Schneider
发明人： Joerg Vollrath , Marcin Gnat , Ralf Schneider
IPC分类号： G01R31/26
CPC分类号： G11C29/56 , G01R1/07 , G01R31/2889 , G01R31/318533 , G01R31/31905 , G11C29/48 , G11C2029/5602 , H01L2224/4824
摘要： An interface between a test access port of an integrated circuit chip and a test equipment, which is designed to perform a functional test of the chip, is provided. The interface includes electric pads on either sides of the chip and the test equipment. The pads are arranged to interact by means of capacitive coupling, when a test data signal is input to one of the pads. Preferably, both pads are connected with either a receiver or a driver depending on the direction of the data flow. The electric pads relating to the chip's side may be arranged within the wiring substrate of a chip package, particularly along edge portion of the substrate, which encompasses an inner portion of the substrate, in which a ball-grid-array can be formed.
摘要翻译： 提供集成电路芯片的测试访问端口和被设计用于执行芯片的功能测试的测试设备之间的接口。 接口包括芯片两侧的电焊盘和测试设备。 当测试数据信号被输入到其中一个焊盘时，焊盘被布置成通过电容耦合相互作用。 优选地，两个焊盘根据数据流的方向与接收器或驱动器连接。 与芯片侧相关的电焊盘可以布置在芯片封装的布线基板内，特别是沿着基板的边缘部分，其包围可以形成球栅阵列的基板的内部。
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15.发明授权Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier 失效具有用于产生用于读/写放大器的电压源的电压发生器电路的集成存储器公开(公告)号：US07068546B2
公开(公告)日：2006-06-27
申请号：US10815856
申请日：2004-04-02
申请人： Ralf Schneider , Joerg Vollrath , Marcin Gnat
发明人： Ralf Schneider , Joerg Vollrath , Marcin Gnat
CPC分类号： G11C11/4091 , G11C7/06 , G11C2207/065
摘要： An integrated memory contains a memory cell array, which has word lines and bit lines, and a read/write amplifier, which is connected to the bit lines for the assessing and amplifying data signals. A voltage generator circuit generates a voltage supply for application to the read/write amplifier. A potential difference is applied to the read/write amplifier using different supply potentials. The voltage generator circuit increases the potential difference applied to the read/write amplifier for a limited period of time during an assessment and amplification operation of the read/write amplifier. Charge-dependent control is implemented in the voltage generator circuit. An assessment and amplification operation can be carried out at a comparatively high switching speed and a low power consumption is possible.
摘要翻译： 集成存储器包含具有字线和位线的存储单元阵列以及连接到位线用于评估和放大数据信号的读/写放大器。 电压发生器电路产生用于施加到读/写放大器的电压源。 使用不同的电源电位对读/写放大器应用电位差。 在读/写放大器的评估和放大操作期间，电压发生器电路在施加到读/写放大器的电位差在一段有限的时间内增加。 电压依赖控制在电压发生器电路中实现。 可以以比较高的开关速度进行评估和放大操作，并且可以实现低功耗。
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16.发明授权Driver circuit having a plurality of drivers for driving signals in parallel 有权具有用于并行驱动信号的多个驱动器的驱动器电路公开(公告)号：US06956404B2
公开(公告)日：2005-10-18
申请号：US10819222
申请日：2004-04-07
申请人： Ralf Schneider , Marcin Gnat , Joerg Vollrath
发明人： Ralf Schneider , Marcin Gnat , Joerg Vollrath
IPC分类号： G11C7/10 , H03K19/00 , H03K19/094
CPC分类号： G11C7/1069 , G11C7/1051 , G11C7/1078 , G11C7/1096 , H03K19/0008 , H03K19/0019
摘要： In a driver circuit having a plurality of drivers for driving signals in parallel, the drivers are each connected to an input signal line for receiving a respective input signal and to an output signal line for outputting a respective driven output signal. An output signal line of one of the drivers may be connected, via a switch or switching means, to an output signal line of another of the drivers. A control circuit is connected to one of the drivers and is used to drive the switch or switching means in such a manner that the switching means can be activated, for charge equalization, by the control circuit following a driving operation in one of the drivers. A respective associated memory circuit, by which an associated logic circuit for driving one of the switch or switching means is connected to the relevant output signal line, is connected to the respective output signal line. Overall power consumption of the driver circuit can be minimized.
摘要翻译： 在具有用于并行驱动信号的多个驱动器的驱动器电路中，驱动器各自连接到用于接收相应输入信号的输入信号线和用于输出相应的驱动输出信号的输出信号线。 驱动器之一的输出信号线可以经由开关或开关装置连接到另一个驱动器的输出信号线。 控制电路连接到其中一个驱动器，并且用于驱动开关或开关装置，使得开关装置可以在其中一个驱动器中的驱动操作之后被控制电路激活以用于充电均衡。 相关联的存储器电路通过其连接到相应的输出信号线，用于驱动开关或开关装置中的一个的相关联的逻辑电路连接到相关的输出信号线。 驱动电路的整体功耗可以最小化。
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公开(公告)号：US20050229054A1
公开(公告)日：2005-10-13
申请号：US11086655
申请日：2005-03-23
CPC分类号： G11C29/50012 , G01R31/3016 , G11C29/02
摘要： An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.
摘要翻译： 可以在正常运行状态和测试运行状态下运行的集成半导体存储器包括具有用于施加输入信号的输入端的电流脉冲电路。 电流脉冲电路经由用于承载电流的互连件连接到输出端子。 在测试操作状态下，当前脉冲电路在第一测试周期中产生具有第一预定持续时间的至少一个第一电流脉冲，以及在随后的第二测试周期中具有第二未知持续时间的至少一个第二电流脉冲。 除了在正常操作状态下在互连上流动的第一电流之外，第二电流在第一测试周期期间在互连上流动，并且第三电流在测试操作状态期间在第二测试周期期间流动。
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公开(公告)号：US20050225917A1
公开(公告)日：2005-10-13
申请号：US11100617
申请日：2005-04-07
IPC分类号： G11C29/12 , H01L21/66 , H01L23/58 , H01L27/108 , H02H9/04
CPC分类号： G11C29/12005 , G11C29/12
摘要： Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.
摘要翻译： 集成半导体电路，特别是动态随机存取存储器包括用于从外部施加的电源电压产生内部电压电平的多个发生器电路。 在测试期间，内部电压电平由发生器电路输出端产生的输出电压改变为外部施加的测试电压。 如果测试电压超出公差范围，则半导体电路可能被破坏。 与发生器电路并联连接的保护电路限制输出电压。
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19.发明申请公开(公告)号：US20080151594A1
公开(公告)日：2008-06-26
申请号：US11958639
申请日：2007-12-18
申请人： Joerg Vollrath
发明人： Joerg Vollrath
CPC分类号： G11C17/16 , G11C17/165 , G11C29/006 , G11C29/56 , G11C2207/2254
摘要： A semiconductor device with a plurality of one time programmable elements and to a method for programming a semiconductor device, and to a method for operating a semiconductor device is disclosed. One embodiment provides a method for programming a semiconductor device comprising a plurality of one time programmable elements that form a group of one time programmable elements. The one time programmable elements of the group are left in a non-programmed state if a first information is to be stored by the group. A first one time programmable element of the group is programmed if a second information differing from the first information is to be stored by the group.
摘要翻译： 公开了一种具有多个一次可编程元件的半导体器件和用于编程半导体器件的方法以及用于操作半导体器件的方法。 一个实施例提供了一种用于编程半导体器件的方法，该半导体器件包括形成一组一次可编程元件的多个一次可编程元件。 如果要由组存储第一信息，则该组的一次可编程元件保持在非编程状态。 如果组中存储与第一信息不同的第二信息，则对该组的第一个一次可编程元件进行编程。
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20.发明授权公开(公告)号：US07051253B2
公开(公告)日：2006-05-23
申请号：US09931125
申请日：2001-08-16
申请人： Randall Rooney , Joerg Vollrath
发明人： Randall Rooney , Joerg Vollrath
IPC分类号： G11C29/00
CPC分类号： G11C29/10
摘要： According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses. The method executes a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test. The method includes determining a fail string for the device including pass/fail results for the test pattern, and combining the pass/fail results in the fail string.
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