公开(公告)号：US06268634B1

公开(公告)日：2001-07-31

申请号：US09178225

申请日：1998-10-23

申请人： Mark I. Gardner ,  H. Jim Eulford, Jr. ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Eulford, Jr. ,  Charles E. May

IPC分类号： H01L2976

CPC分类号： H01L21/28132 ,  Y10S257/90

摘要： A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.

摘要翻译： 公开了一种用于制造具有小于使用普通光刻技术可分辨长度的沟道长度的晶体管的工艺。 在轻掺杂的半导体衬底上形成栅氧化层。 然后在栅极氧化物层上沉积栅极导体层。 栅极导体层的上表面包括由间隔开的一对目标区域横向限定的未来导体区域，其中间隔开的一对目标区域之间的横向距离优选地以光刻阈值选择。 将氮气注入到间隔开的一对目标区域中，以在栅极导体层内形成间隔开的一对含氮区域，从而在栅极导体层中限定无氮区域。 热退火降低了无氮区域的宽度。 然后在整个半导体拓扑上生长可变厚度的氧化物层，并进行各向异性蚀刻，以在较宽的无氮区域上形成氧化物掩模。 然后去除不被氧化物掩模覆盖的栅极导体层的部分，留下宽度窄的无氮区域作为宽度低于光刻阈值的栅极导体。

公开(公告)号：US06258646B1

公开(公告)日：2001-07-10

申请号：US09149631

申请日：1998-09-08

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

IPC分类号： H01L218238

CPC分类号： H01L27/092 ,  H01L21/823814 ,  Y10S257/90

摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.

摘要翻译： 提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。 首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。 首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。 与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。 通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。

公开(公告)号：US06248252B1

公开(公告)日：2001-06-19

申请号：US09256541

申请日：1999-02-24

申请人： Thien T. Nguyen ,  Mark I. Gardner

发明人： Thien T. Nguyen ,  Mark I. Gardner

IPC分类号： C23F100

CPC分类号： C23F4/00 ,  H01L21/32136 ,  H01L21/76838

摘要： Methods of fabricating interconnects of aluminum and aluminum alloys are provided. In one aspect, a method is provided for fabricating an interconnect of aluminum-containing material on a surface. A layer of aluminum-containing material is deposited on the surface. The layer of aluminum-containing material is masked with selected portions thereof left exposed. A first etch of the exposed portions is performed in a plasma ambient containing BCl3, Cl2, N2 and CF4 to establish a plurality of trenches having inwardly sloping sidewalls. An overetch of the exposed portions is performed to the surface in a plasma ambient. High aspect ratio lines may be formed with sloped sidewalls that facilitate subsequent interlevel dielectric formation.

摘要翻译： 提供制造铝和铝合金互连的方法。 在一个方面，提供了一种用于在表面上制造含铝材料的互连的方法。 一层含铝材料沉积在表面上。 含铝材料层被掩盖，其中所选择的部分露出。 暴露部分的第一蚀刻在含有BCl 3，Cl 2，N 2和CF 4的等离子体环境中进行，以建立具有向内倾斜侧壁的多个沟槽。 在等离子体环境中对表面进行暴露部分的过蚀刻。 高纵横比线可以形成有倾斜的侧壁，其有助于随后的层间电介质形成。

公开(公告)号：US06245652B1

公开(公告)日：2001-06-12

申请号：US09598531

申请日：2000-06-21

申请人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford

发明人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford

IPC分类号： H01L213205

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention is directed to a semiconductor device having an ultra thin, reliable gate dielectric and a method for making same. In one illustrative embodiment, the present method comprises forming a first layer of nitrogen doped silicon dioxide above a semiconducting substrate, reducing the thickness of the first layer, forming a second layer comprised of a material having a dielectric constant greater than seven above the first layer of silicon dioxide. The method further comprises forming a third layer comprised of a gate conductor material above the second layer, and patterning the first, second and third layers to define a gate conductor and a composite gate dielectric comprised of the first and second layers, and forming at least one source/drain region. The semiconductor device has a composite gate dielectric comprised of a first process layer comprised of a nitrogen doped oxide and a second process layer comprised of a material having a dielectric constant greater than seven. The device further comprises a gate conductor positioned above the composite gate dielectric, and at least one source/drain region formed in the substrate.

摘要翻译： 本发明涉及具有超薄，可靠的栅极电介质的半导体器件及其制造方法。 在一个说明性实施例中，本方法包括在半导体衬底上形成氮掺杂二氧化硅的第一层，减小第一层的厚度，形成第二层，第二层由介电常数大于第一层以上的材料构成 的二氧化硅。 该方法还包括在第二层上形成由栅极导体材料构成的第三层，以及对第一层，第二层和第三层进行构图以限定由第一层和第二层构成的栅极导体和复合栅极电介质，并形成至少 一个源/漏区。 该半导体器件具有复合栅极电介质，该复合栅极电介质由包含氮掺杂氧化物的第一工艺层和由介电常数大于7的材料构成的第二工艺层组成。 该器件还包括位于复合栅极电介质上方的栅极导体，以及形成在衬底中的至少一个源极/漏极区。

公开(公告)号：US06232637B1

公开(公告)日：2001-05-15

申请号：US09249954

申请日：1999-02-12

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L31036

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure. Select portions of the primary and secondary interlevel dielectrics are then removed to expose one of the junctions and a portion of the doped polysilicon structure arranged proximate this junction. An interconnect is formed contiguously between the junction and the polysilicon structure by depositing a conductive material within the removed portions.

摘要翻译： 提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构。 升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。 升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。 提供晶体管，其包括在一对结之间间隔开的栅极导体。 在晶体管两端沉积初级层间电介质。 在初级层间电介质的上表面的选择部分内形成多晶硅结构。 多晶硅结构是距离晶体管的上方和横向距离之间的间隔距离。 将掺杂剂注入到多晶硅结构中。 次级层间电介质沉积在初级层间电介质和掺杂多晶硅结构之间。 选择部分初级和次级层间电介质然后被去除以暴露出一个结点，并且掺杂多晶硅结构的一部分布置在该结附近。 通过在去除的部分内沉积导电材料，在结和多晶硅结构之间连续地形成互连。

公开(公告)号：US06225201B1

公开(公告)日：2001-05-01

申请号：US09433801

申请日：1999-11-03

申请人： Mark I. Gardner ,  Derrick J. Wristers ,  Jon D. Cheek ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Derrick J. Wristers ,  Jon D. Cheek ,  Thomas E. Spikes, Jr.

IPC分类号： H01L213205

CPC分类号： H01L29/517 ,  H01L21/0338 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/2815 ,  H01L21/28194 ,  H01L21/31144 ,  H01L29/6659 ,  H01L29/66659 ,  Y10S438/947

摘要： An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length dictated by the width of a sidewall spacer which either embodies a gate conductor for the transistor or is used to pattern an underlying gate conductor. In one embodiment, the sidewall spacers are formed upon and extending laterally from the opposed sidewall surfaces of a sacrificial material. The sidewall surfaces of the sacrificial material are defined by forming the sacrificial material within an opening interposed laterally between vertically extending sidewalls which bound a gate dielectric. An upper portion of the gate dielectric is removed to partially expose the sidewall surfaces arranged at the periphery of the sacrificial material. Polysilicon spacers are formed exclusively upon the sidewall surfaces of the sacrificial material to define a pair of gate conductors having relatively small lateral widths. Portions of the gate dielectric not arranged exclusively beneath the gate conductors may be selectively removed. In another embodiment, sidewall spacers are used to protect select regions of a polysilicon gate material arranged exclusively underneath the spacers from being etched. The sidewall spacers are formed upon and extending laterally from sidewall surfaces arranged at the periphery of an opening which extends through a masking or sacrificial material to an underlying polysilicon gate material. The sidewall spacers are sacrificial in that they are removed from the semiconductor topography after they have served their purpose of masking the underlying polysilicon gate material.

摘要翻译： 提供了一种集成电路制造工艺，用于形成具有由侧壁间隔物的宽度所规定的超短沟道长度的晶体管，该侧壁间隔物体现了晶体管的栅极导体或用于对下面的栅极导体进行图案化。 在一个实施例中，侧壁间隔件形成在牺牲材料的相对的侧壁表面上并从牺牲材料的相对侧壁表面延伸。 牺牲材料的侧壁表面通过在封闭栅极电介质的垂直延伸侧壁之间横向插入的开口内形成牺牲材料来限定。 去除栅极电介质的上部以部分地暴露设置在牺牲材料的周边处的侧壁表面。 专门在牺牲材料的侧壁表面上形成多晶硅间隔物，以限定具有相对小的横向宽度的一对栅极导体。 可以选择性地去除不排列在栅极导体下方的栅极电介质的部分。 在另一个实施例中，侧壁间隔件用于保护专门在间隔物下方布置的多晶硅栅极材料的选择区域被蚀刻。 侧壁间隔件形成在侧壁表面上并且从侧壁表面延伸出来，该侧壁表面布置在开口的周边，该开口延伸穿过掩模或牺牲材料到下面的多晶硅栅极材料。 侧壁间隔物是牺牲的，因为它们已经用于掩盖下面的多晶硅栅极材料的目的，从半导体拓扑图中去除它们。

公开(公告)号：US06218251B1

公开(公告)日：2001-04-17

申请号：US09187894

申请日：1998-11-06

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21336

CPC分类号： H01L29/66598 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/7835

摘要： In an IGFET device having at least one source/drain region with a lightly-doped sub-region proximate a channel region, the source/drain regions are formed by first implanting ions with parameters to form lightly-doped source/drain regions. A high density plasma deposition provides at least one spacer having preselected characteristics. As a result of the spacer characteristics, an ion implantation with parameters to form normally-doped source/drain regions is shadowed by the spacer. A portion of the source/drain region shadowed by the spacer results in a lightly-doped source/drain sub-region proximate the channel region. According to a second embodiment of the invention, the ion implantation resulting in the lightly-doped source/drain regions is eliminated. Instead, the spacer(s) formed by the high density plasma deposition and subsequent etching process only partially shadows the ion implantation that would otherwise result in normal doping of the source/drain regions. The parameters of the spacer(s) resulting from the high density plasma deposition and subsequent etching process result in a lightly-doped source/drain sub-region proximate the channel region. The shadowing of the spacer decreases with distance from the gate structure and results in a normal doping level for the portion of the source/drain terminal not shadowed by the spacer.

摘要翻译： 在具有至少一个具有靠近沟道区的轻掺杂子区域的源极/漏极区域的IGFET器件中，通过首先用参数注入离子以形成轻掺杂的源极/漏极区域来形成源极/漏极区域。 高密度等离子体沉积提供至少一个具有预选特性的间隔物。 作为间隔物特性的结果，具有形成常态掺杂源极/漏极区域的参数的离子注入被间隔物遮蔽。 由间隔物遮蔽的源极/漏极区域的一部分导致靠近沟道区域的轻掺杂源极/漏极子区域。 根据本发明的第二实施例，消除了导致轻掺杂源/漏区的离子注入。 替代地，通过高密度等离子体沉积和随后的蚀刻工艺形成的间隔物仅部分地影响否则将导致源/漏区的正常掺杂的离子注入。 由高密度等离子体沉积和随后的蚀刻工艺产生的间隔物的参数导致靠近沟道区的轻掺杂的源极/漏极子区域。 间隔物的阴影随着与栅极结构的距离而减小，并且导致源极/漏极端子的未被间隔物遮蔽的部分的正常掺杂水平。

公开(公告)号：US06204130B1

公开(公告)日：2001-03-20

申请号：US08924455

申请日：1997-08-29

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659

摘要： A semiconductor device having a reduced polysilicon gate electrode width and a process for manufacturing such a device is provided. Consistent with the present invention a semiconductor device is formed by forming an insulating film selective to oxide etchant over a substrate. At least one polysilicon block is formed over the insulating film. The polysilicon block is oxidized to grow an oxide layer on exposed surfaces of the polysilicon block and thereby reduce the width of the polysilicon block. The oxide layer is then removed to form a gate electrode with the remaining portion of the polysilicon block. In this manner, gate electrodes having widths smaller than the resolution of current etching techniques can be formed. In accordance with one aspect of the invention, the polysilicon gate electrode has a width less than about 0.15 microns. In accordance with another aspect, the insulating layer selective to oxide etchant is formed from a high permittivity material, such as a barium strontium titanate oxide.

摘要翻译： 提供具有降低的多晶硅栅电极宽度的半导体器件和用于制造这种器件的工艺。 根据本发明，通过在衬底上形成对氧化物蚀刻剂有选择性的绝缘膜来形成半导体器件。 在绝缘膜上形成至少一个多晶硅块。 多晶硅块被氧化以在多晶硅块的暴露表面上生长氧化物层，从而减小多晶硅块的宽度。 然后去除氧化物层以形成具有多晶硅块的剩余部分的栅电极。 以这种方式，可以形成具有小于当前蚀刻技术的分辨率的宽度的栅电极。 根据本发明的一个方面，多晶硅栅电极具有小于约0.15微米的宽度。 根据另一方面，对氧化物蚀刻剂选择性的绝缘层由诸如钛酸锶钡氧化物的高介电常数材料形成。

公开(公告)号：US06200865B1

公开(公告)日：2001-03-13

申请号：US09205443

申请日：1998-12-04

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr.

IPC分类号： H01L21336

CPC分类号： H01L29/66537 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66825

摘要： A semiconductor device is provided and formed using self-aligned low-resistance gates within a metal-oxide semiconductor (MOS) process. A sacrificial dielectric gate structure is formed on a semiconductor substrate instead of a conventional gate dielectric/gate conductor stack. After forming junction regions within a semiconductor substrate, the gate structure is removed to form a trench within a dielectric formed above the substrate. A low-resistance gate material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The gate material can take various forms, including a single layer or multiple metal and/or dielectric layers interposed throughout the as-filled trench. The gate formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.

摘要翻译： 在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻栅极提供并形成半导体器件。 在半导体衬底上形成牺牲电介质栅极结构，而不是传统的栅极介质/栅极导体堆叠。 在半导体衬底中形成结区之后，去除栅极结构，以在衬底之上形成的电介质内形成沟槽。 然后可以在沟槽内，即在去除栅极导体的区域中布置低电阻栅极材料。 栅极材料可以采取各种形式，包括插入整个填充沟槽中的单层或多个金属和/或介电层。 栅极形成发生在高温循环之后，通常与激活以前注入的结或生长的栅极电介质相关联。 因此，可以使用诸如铜或铜合金的低温金属。

公开(公告)号：US06191446B1

公开(公告)日：2001-02-20

申请号：US09035780

申请日：1998-03-04

申请人： Mark I. Gardner ,  John J. Bush ,  Jon D. Cheek

发明人： Mark I. Gardner ,  John J. Bush ,  Jon D. Cheek

IPC分类号： H01L2976

CPC分类号： H01L29/66666 ,  H01L29/665 ,  H01L29/7827 ,  Y10S257/90

摘要： A process is provided for forming a transistor in which the channel length is controlled by the depth of a trench etched into a semiconductor substrate. A masking layer extending across the substrate and a portion of the substrate are etched simultaneously to form the trench. A gate dielectric is formed upon the opposed sidewall surfaces of the trench. A pair of gate conductors are then formed upon the exposed lateral surfaces of the gate dielectric and the masking layer. Subsequently, an unmasked region of the substrate underneath the trench is implanted with dopant species and then annealed to form a source junction. The anneal temperature is preferably sufficient to cause the dopant species in the source junction to migrate laterally past the opposed sidewall surfaces of the trench. Drain junctions may subsequently be formed within the substrate a spaced distance above the source region on opposite sides of the trench. The physical channel length of the resulting transistors is thus defined as the distance between a source region and an overlying drain region. The channel of each transistor is spaced laterally from a gate conductor by a gate dielectric.

摘要翻译： 提供了一种用于形成晶体管的工艺，其中沟道长度被蚀刻到半导体衬底中的沟槽的深度控制。 同时蚀刻跨过衬底延伸的掩模层和衬底的一部分以形成沟槽。 栅极电介质形成在沟槽的相对的侧壁表面上。 然后在栅极电介质和掩蔽层的暴露的侧表面上形成一对栅极导体。 随后，在沟槽下面的衬底的未掩蔽区域注入掺杂剂种类，然后退火以形成源极结。 退火温度优选足以使源极结中的掺杂物质横向迁移通过沟槽的相对的侧壁表面。 随后可以在衬底的相对侧上的源极区域上方间隔开距离处形成漏极结。 因此，所得晶体管的物理沟道长度被定义为源极区域和上覆漏极区域之间的距离。 每个晶体管的沟道通过栅极电介质与栅极导体横向隔开。