公开(公告)号：US5223736A

公开(公告)日：1993-06-29

申请号：US704232

申请日：1991-05-22

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/763

CPC classification number: H01L21/763

Abstract: A structure for and method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30. Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

Abstract translation: 本文公开了一种在半导体本体中形成沟槽的结构和方法。 在要形成沟槽26的n阱8的一部分上生长场氧化物16。 氮化物层20和TEOS氧化物层22沉积。 抗蚀剂24被图案化，TEOS层22，氮化物层20和场氧化物层16被蚀刻。 去除抗蚀剂24，并且通过n阱8蚀刻沟槽26并进入衬底4.然后在沟槽26的侧壁上生长薄氧化物28.多晶硅沉积到沟槽26中并被回蚀以形成多晶硅插塞30.侧壁氧化物32 ，以防止沟槽26的形状中的空隙沿着沟槽26的外边缘形成在多晶硅插塞30的顶部上。为了防止泄漏到沟槽26中，厚的热氧化物盖34生长在沟槽26上。

公开(公告)号：US5145799A

公开(公告)日：1992-09-08

申请号：US647579

申请日：1991-01-30

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/02 ,  H01L21/8244

CPC classification number: H01L28/40 ,  H01L27/11

Abstract: This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50, 52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors, whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.

Abstract translation: 这是一个SRAM单元，单元可以包括：两个NMOS驱动晶体管; 两个PMOS负载晶体管; 第一和第二底部电容器板50,52，其中第一板50位于驱动晶体管之一的栅极34上，而第二板52位于另一个驱动晶体管的栅极40之上; 在第一和第二底部电容器板上的电介质材料层68; 以及在电介质层上的第一和第二顶部电容器板20,26，其中第一顶部电容器20板形成负载晶体管中的一个的栅极，并且与第二顶部电容器板26形成另一个负载晶体管的栅极，由此 电容器板在驱动晶体管的栅极之间形成两个交叉耦合的电容器，并且增强了电池的稳定性。 这也是形成SRAM单元的方法。

公开(公告)号：US5079180A

公开(公告)日：1992-01-07

申请号：US568305

申请日：1990-08-16

Applicant: Mark S. Rodder ,  Richard A. Chapman

Inventor： Mark S. Rodder ,  Richard A. Chapman

IPC: H01L21/336 ,  H01L29/08

CPC classification number: H01L29/66628 ,  H01L29/0847

Abstract: A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).

Abstract translation: 提供了一个升高的源极/漏极晶体管，其具有与晶体管栅极（48）相邻的薄的侧壁间隔绝缘体（54）。 第一侧壁间隔物（64）邻近薄侧壁间隔绝缘体（54）和升高的源/漏区（60）设置。 第二侧壁间隔物（66）形成在场绝缘区域（44）和凸起源极/漏极区域（60）之间的界面处。

公开(公告)号：US4999690A

公开(公告)日：1991-03-12

申请号：US452855

申请日：1989-12-19

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/78618 ,  H01L29/41733

Abstract: A thin film field effect transistor and method for forming the same are disclosed. Conductive moat bodies 16 and 18 are formed on a surface 12 of an insulator substrate 10. A semiconductor channel layer 20 is formed covering the moat bodies 16 and 18 and the surface 12. A gate insulator layer 22 is formed covering the channel layer 20 between the moat bodies 16 and 18. A gate conductor 26 is formed outwardly from the gate insulator layer 22. Moat bodies 16 and 18 provide efficient contact points for a source contact 56 and a drain contact 60. Additionally, moat bodies 16 and 18 provide additional material from which silicide bodies 48 and 52 may be optionally formed.

Abstract translation: 公开了薄膜场效应晶体管及其形成方法。 导电沟槽体16和18形成在绝缘体基板10的表面12上。形成覆盖沟槽体16,18和表面12的半导体沟道层20.形成栅极绝缘体层22，覆盖沟道层20之间 护城河主体16和18.门导体26从栅极绝缘体层22向外形成。护城河体16和18为源接触56和排水接触60提供有效的接触点。另外，护城河体16和18提供额外的 可以任选地形成硅化物体48和52的材料。

公开(公告)号：US09917158B2

公开(公告)日：2018-03-13

申请号：US14942193

申请日：2015-11-16

Applicant: Jorge A. Kittl ,  Borna Josip Obradovic ,  Robert Christopher Bowen ,  Mark S. Rodder

Inventor： Jorge A. Kittl ,  Borna Josip Obradovic ,  Robert Christopher Bowen ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L21/285 ,  H01L29/45 ,  H01L29/08

CPC classification number: H01L29/267 ,  H01L21/28575 ,  H01L29/0847 ,  H01L29/452 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV.

公开(公告)号：US20160163796A1

公开(公告)日：2016-06-09

申请号：US14952152

申请日：2015-11-25

Applicant: Borna J. Obradovic ,  Ryan Hatcher ,  Robert C. Bowen ,  Mark S. Rodder

Inventor： Borna J. Obradovic ,  Ryan Hatcher ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/0676 ,  B82B3/0014 ,  B82Y10/00 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/16 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal.

Abstract translation: 器件可以包括纳米片状场效应晶体管（FET），其可以包括衬底，在衬底的表面上掺杂有杂质的阱，包括多个堆叠的纳米片，沟道，导电材料和 隔离层 多个堆叠的纳米片的一部分可以包括半导体材料，其可掺杂与阱的杂质相同的导电类型的杂质。 导电材料可以与多个纳米片相邻，并且可以将多个纳米片中的一个纳米片电连接到该孔。 隔离层可以将孔与功函数金属电绝缘。

公开(公告)号：US20150145003A1

公开(公告)日：2015-05-28

申请号：US14534453

申请日：2014-11-06

Applicant: Mark S. Rodder ,  Borna J. Obradovic ,  Robert C. Bowen

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Robert C. Bowen

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848

Abstract: FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side.

Abstract translation: 提供FinFET半导体器件及其形成方法。 finFET半导体器件可以包括绝缘体层，绝缘体层上的底部半导体层，底部半导体层上的沟道鳍片，底部半导体层上的源极区域和与沟道鳍片的第一侧相邻的源区域，以及漏极区域 在底部半导体层上并且与第一侧相对的沟槽的第二侧相邻。

公开(公告)号：US07459734B2

公开(公告)日：2008-12-02

申请号：US10846741

申请日：2004-05-14

Applicant: Keith A. Joyner ,  Mark S. Rodder

Inventor： Keith A. Joyner ,  Mark S. Rodder

IPC: H01L31/062 ,  H01L31/113

CPC classification number: H01L21/76897 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract translation: 一种制造晶体管的方法，包括：提供具有第一表面的半导体层，设置在第一表面上的电介质层，设置在电介质层上的栅电极，与栅电极的至少一部分相邻的绝缘层的晶体管组件， 以及邻近绝缘层的至少一部分的氮化物间隔层。 该方法还包括在第一表面的一部分上沉积将与半导体层反应以形成硅化物并除去未反应材料的材料。 该方法还包括蚀刻氮化物间隔层，沉积与氮化物间隔层的至少一部分相邻的预金属间隔层和至少部分第一表面，蚀刻去除前金属间隔层的一部分以暴露部分 第一表面的硅化部分，并与第一表面的硅化部分形成接触。

公开(公告)号：US07160782B2

公开(公告)日：2007-01-09

申请号：US10870016

申请日：2004-06-17

Applicant: Rick L. Wise ,  Mark S. Rodder

Inventor： Rick L. Wise ,  Mark S. Rodder

IPC: H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/76237 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract translation: 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁中的注入缓冲层（133）。 沟槽隔离结构（130）还包括位于注入缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

公开(公告)号：US06686300B2

公开(公告)日：2004-02-03

申请号：US10055262

申请日：2001-10-25

Applicant: Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

Inventor： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

IPC: H01L21302

CPC classification number: H01L29/4238 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/1033 ,  Y10S438/945

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.