公开(公告)号：US20140021571A1

公开(公告)日：2014-01-23

申请号：US14009834

申请日：2012-04-01

Applicant: Xiaofeng Lei ,  Insik Jin ,  James Deak ,  Weifeng Geza Shen ,  Mingfeng Liu ,  Songsheng Xue

Inventor： Xiaofeng Lei ,  Insik Jin ,  James Deak ,  Weifeng Geza Shen ,  Mingfeng Liu ,  Songsheng Xue

IPC: H01L43/02

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G01B7/30 ,  G01R33/0052 ,  G01R33/093 ,  G01R33/098 ,  G11B5/3909 ,  G11B5/3993 ,  G11B2005/3996 ,  H01L43/02 ,  H01L43/08

Abstract: The present invention discloses a design and manufacturing method for a single-chip magnetic sensor bridge. The sensor bridge comprises four magnetoresistive elements. The magnetization of the pinned layer of each of the four magnetoresistive elements is set in the same direction, but the magnetization directions of the free layers of the magnetoresistive elements on adjacent arms of the bridge are set at different angles with respect to the pinned layer magnetization direction. The absolute values of the angles of the magnetization directions of the free layers of all four magnetoresistive elements are the same with respect with their pinning layers. The disclosed magnetic biasing scheme enables the integration of a push-pull Wheatstone bridge magnetic field sensor on a single chip with better performance, lower cost, and easier manufacturability than conventional magnetoresistive sensor designs.

Abstract translation: 本发明公开了一种单芯片磁传感器桥的设计和制造方法。 传感器桥包括四个磁阻元件。 四个磁阻元件中的每一个的钉扎层的磁化被设定在相同的方向上，但是桥的相邻臂上的磁阻元件的自由层的磁化方向相对于被钉扎层磁化被设定在不同的角度 方向。 所有四个磁阻元件的自由层的磁化方向的角度的绝对值与它们的钉扎层相同。 所公开的磁偏置方案使得能够将单个芯片上的推挽惠斯通电桥磁场传感器与传统的磁阻传感器设计相比具有更好的性能，更低的成本和更易于制造的能力。

公开(公告)号：US20060076635A1

公开(公告)日：2006-04-13

申请号：US11295177

申请日：2005-12-05

Applicant: Hasan Nejad ,  James Deak

Inventor： Hasan Nejad ,  James Deak

IPC: H01L43/00

CPC classification number: H01L27/222

Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

Abstract translation: 本发明包括在一对导线之间包括MRAM器件的结构。 每个导线可以产生包围MRAM装置的至少一部分的磁场。 每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。 本发明还包括形成包含MRAM器件的组件的方法。 在衬底上形成多个MRAM器件。 导电材料形成在MRAM器件上，并被图案化成多条线。 这些线与MRAM器件一一对应，并且彼此间隔开。 在将导电材料图案化成线之后，形成磁性材料以在线之间和线之间的空间内延伸。

公开(公告)号：US20050078512A1

公开(公告)日：2005-04-14

申请号：US10926237

申请日：2004-08-26

Applicant: James Deak

Inventor： James Deak

IPC: G11C11/16 ,  G11C11/15

CPC classification number: G11C11/16

Abstract: A magnetic random access memory (MRAM) is compensated for write current shunting by varying the bit size of each MRAM cell with position along the write line. The MRAM includes a plurality of magnetic tunnel junction memory cells arranged in an array of columns and rows. The width of each memory cell increases along a write line to compensate for write current shunting.

Abstract translation: 磁性随机存取存储器（MRAM）通过沿着写入线的位置改变每个MRAM单元的位大小来补偿写入电流分流。 MRAM包括以列和行阵列排列的多个磁性隧道结存储单元。 每个存储单元的宽度沿写入线增加以补偿写入电流分流。

公开(公告)号：US20050040453A1

公开(公告)日：2005-02-24

申请号：US10920740

申请日：2004-08-17

Applicant: Hasan Nejad ,  James Deak

Inventor： Hasan Nejad ,  James Deak

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/22 ,  H01L29/76 ,  H01L43/12

CPC classification number: H01L27/222

Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

Abstract translation: 本发明包括在一对导线之间包括MRAM器件的结构。 每个导线可以产生包围MRAM装置的至少一部分的磁场。 每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。 本发明还包括形成包含MRAM器件的组件的方法。 在衬底上形成多个MRAM器件。 导电材料形成在MRAM器件上，并被图案化成多条线。 这些线与MRAM器件一一对应，并且彼此间隔开。 在将导电材料图案化成线之后，形成磁性材料以在线之间和线之间的空间内延伸。

公开(公告)号：US20050030786A1

公开(公告)日：2005-02-10

申请号：US10932949

申请日：2004-09-02

Applicant: James Deak

Inventor： James Deak

IPC: G11C11/00 ,  G11C11/16 ,  H01L21/00 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L27/222 ,  G11C11/16

Abstract: Systems, devices and methods are provided for magnetic memory elements with low remanence flux concentrators. Improved bit yield is attributable to reduced remanence in the flux concentrator. Remanence provides the memory element with a biasing magnetic field. The flux concentrator includes anisotropy aligned with an appropriate conductor. One aspect of the present subject matter is a memory cell. One memory cell embodiment includes a magnetic memory element and a flux concentrator operably positioned with respect to a conductor. The conductor is adapted to provide a current-induced magnetic flux to the magnetic memory element. The flux concentrator includes an easy axis of magnetization aligned with the conductor and a hard axis of magnetization orthogonal to the easy axis of magnetization. Other aspects are provided herein.

Abstract translation: 提供了具有低剩磁通量集中器的磁存储器元件的系统，装置和方法。 提高的钻头产量可归因于通量集中器中的剩磁减少。 剩余为存储元件提供偏置磁场。 通量集中器包括与适当导体对准的各向异性。 本主题的一个方面是存储单元。 一个存储单元实施例包括磁性存储元件和相对于导体可操作地定位的磁通集中器。 导体适于向磁存储元件提供电流感应磁通量。 磁通集中器包括与导体对准的易磁化轴和与易磁化轴正交的硬磁化轴。 本文提供了其他方面。

公开(公告)号：US20070020775A1

公开(公告)日：2007-01-25

申请号：US11535456

申请日：2006-09-26

Applicant: Joel Drewes ,  James Deak

Inventor： Joel Drewes ,  James Deak

IPC: H01L21/00 ,  H01L21/336

CPC classification number: H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.

Abstract translation: MRAM器件包括具有由阻挡层隔开的上导电层和下导电层的磁存储单元的阵列。 为了减少跨越存储器单元的阻挡层的电短路的可能性，可以在上导电层周围形成间隔物，并且在已经蚀刻了磁存储单元的层之后，可以将存储单元氧化以转换任何导电颗粒 沿着存储器单元的侧壁沉积作为蚀刻工艺的副产物而形成非导电颗粒。 或者，下导电层可以重复进行部分氧化和部分蚀刻步骤，使得只有非导电颗粒可以作为蚀刻工艺的副产物沿着存储器单元的侧壁被抛出。

公开(公告)号：US20060226458A1

公开(公告)日：2006-10-12

申请号：US11430138

申请日：2006-05-09

Applicant: James Deak

Inventor： James Deak

IPC: H01L29/94

CPC classification number: G11C11/16

Abstract: A magnetic memory element includes a sense structure, a tunnel barrier adjacent the sense structure, and a synthetic antiferromagnet (SAF) adjacent the tunnel barrier on a side opposite the sense structure. The SAF includes an antiferromagnetic structure adjacent a ferromagnetic seed layer. The ferromagnetic seed layer provides a texture so that the antiferromagnetic structure deposited on the ferromagnetic seed layer has reduced pinning field dispersion.

公开(公告)号：US20060192235A1

公开(公告)日：2006-08-31

申请号：US11412582

申请日：2006-04-27

Applicant: Joel Drewes ,  James Deak

Inventor： Joel Drewes ,  James Deak

IPC: H01L29/94 ,  H01L21/00

CPC classification number: H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.

公开(公告)号：US20050242382A1

公开(公告)日：2005-11-03

申请号：US11116874

申请日：2005-04-28

Applicant: James Daughton ,  James Deak ,  Arthur Pohm

Inventor： James Daughton ,  James Deak ,  Arthur Pohm

IPC: H01L21/8246 ,  H01L27/22 ,  H01L29/94

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/16 ,  H01L27/224 ,  H01L43/10

Abstract: A ferromagnetic thin-film based digital memory having a substrate formed of a base supporting an electrically insulating material primary substrate layer in turn supporting a plurality of current control devices each having an interconnection arrangement with each of said plurality of current control devices being separated from one another by spacer material therebetween and being electrically interconnected with information storage and retrieval circuitry. A plurality of bit structures are each supported on and electrically connected to a said interconnection arrangement of a corresponding one of said plurality of current control devices and have magnetic material films in which a characteristic magnetic property is substantially maintained below an associated critical temperature above which such magnetic property is not maintained of which two are separated by at least one intermediate layer of a nonmagnetic material having two major surfaces on opposite sides thereof. A plurality of word line structures located across from a corresponding one of the bit structures on an opposite side of the intermediate layer of a corresponding one of said bit structures from its interconnection arrangement supporting that bit structure. Sufficient electrical current selectively drawn through each of these bit structures as interconnected can cause substantial heating of that bit structure to raise temperatures thereof to have at least one of the magnetic material films therein at least approach its corresponding associated critical temperature while being substantially above temperatures of at least an adjacent said bit structure because of sufficient thermal isolation.

Abstract translation: 一种基于铁磁薄膜的数字存储器，其具有由支撑电绝缘材料主基底层的基底形成的基底，其又支撑多个电流控制装置，每个电流控制装置具有与所述多个电流控制装置中的每一个的互连装置， 另一个通过其间的间隔物材料并且与信息存储和检索电路电互连。 多个位结构分别被支撑在所述多个电流控制装置中的对应的一个电流控制装置的所述互连装置上并与其电连接，并且具有磁性材料膜，其中特性磁性能基本上保持在相关的临界温度以下， 磁性不保持，其中两个被至少一个在其相对侧上具有两个主表面的非磁性材料的中间层隔开。 多个字线结构，位于相对应的所述位结构的中间层的相对侧上的对应的一个位线结构，以及支撑该位结构的互连布置。 通过互连的这些位结构中的每一个选择性地抽出足够的电流可引起该位结构的实质加热以升高其温度，使其中的至少一个磁性材料膜至少接近其对应的相关临界温度，同时基本上高于 至少相邻的所述位结构由于足够的热隔离。

公开(公告)号：US20050146912A1

公开(公告)日：2005-07-07

申请号：US10745531

申请日：2003-12-29

Applicant: James Deak

Inventor： James Deak

IPC: G11C11/16 ,  G11C11/22

CPC classification number: G11C11/16

Abstract: A magnetic memory element includes a sense structure, a tunnel barrier adjacent the sense structure, and a synthetic antiferromagnet (SAF) adjacent the tunnel barrier on a side opposite the sense structure. The SAF includes an antiferromagnetic structure adjacent a ferromagnetic seed layer. The ferromagnetic seed layer provides a texture so that the antiferromagnetic structure deposited on the ferromagnetic seed layer has reduced pinning field dispersion.

Abstract translation: 磁存储元件包括感测结构，与感测结构相邻的隧道势垒，以及与感测结构相对的一侧与隧道势垒相邻的合成反铁磁体（SAF）。 SAF包括与铁磁种子层相邻的反铁磁结构。 铁磁种子层提供纹理，使得沉积在铁磁种子层上的反铁磁结构具有减少的钉扎场分散。