公开(公告)号：US20060194446A1

公开(公告)日：2006-08-31

申请号：US11415320

申请日：2006-05-01

Applicant: Kevin Beaman ,  John Moore ,  Ronald Weimer

Inventor： Kevin Beaman ,  John Moore ,  Ronald Weimer

IPC: H01L23/52 ,  H01L21/31

CPC classification number: H01L21/28185 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/3144 ,  H01L29/518 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of adjusting the threshold voltage of semiconductor devices by incorporating nitride into the isolation layer so as to decrease the mobility of charge carriers and thereby increase the threshold voltage required to activate the device. The nitrogen incorporation method may comprise of decoupled plasma nitridization (DPN) and the DPN can be performed in-situ during gate oxide formation. The amount of threshold voltage can be varied by adjusting the DPN treatment time and processing parameters.

Abstract translation: 一种通过将氮化物结合到隔离层中来调节半导体器件的阈值电压的方法，以便降低电荷载流子的迁移率，从而增加激活器件所需的阈值电压。 氮掺杂方法可以包括去耦等离子体氮化（DPN），并且可以在栅极氧化物形成期间原位进行DPN。 可以通过调整DPN处理时间和处理参数来改变阈值电压量。

公开(公告)号：US20060011969A1

公开(公告)日：2006-01-19

申请号：US11205772

申请日：2005-08-17

Applicant: Ronald Weimer ,  Don Powell ,  John Moore ,  Jeff McKee

Inventor： Ronald Weimer ,  Don Powell ,  John Moore ,  Jeff McKee

IPC: G11C16/04 ,  H01L29/788

CPC classification number: H01L29/517 ,  H01L21/28273 ,  H01L29/511

Abstract: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

公开(公告)号：US20060289949A1

公开(公告)日：2006-12-28

申请号：US11513658

申请日：2006-08-31

Applicant: Ronald Weimer

Inventor： Ronald Weimer

IPC: H01L29/94

CPC classification number: H01L21/28185 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.

公开(公告)号：US20060258157A1

公开(公告)日：2006-11-16

申请号：US11127945

申请日：2005-05-11

Applicant: Ronald Weimer

Inventor： Ronald Weimer

IPC: H01L21/44

CPC classification number: C23C16/45546 ,  C23C16/4557 ,  C23C16/45578

Abstract: The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is provided between a stack of semiconductor substrates and a precursor inlet, and configured so that problematic side reactions occur proximate the heated surface rather than proximate the semiconductor substrates. The precursor inlet can be one of a plurality of precursor inlets, and the heated surface can be one of a plurality of heated surfaces.

Abstract translation: 本发明包括可以在原子层沉积或化学气相沉积期间使用的沉积方法和装置。 加热表面设置在半导体衬底的堆叠和前体入口之间，并且被配置为使得有问题的副反应发生在加热表面附近，而不是靠近半导体衬底。 前体入口可以是多个前体入口之一，并且加热的表面可以是多个加热表面中的一个。

公开(公告)号：US20060194452A1

公开(公告)日：2006-08-31

申请号：US11415011

申请日：2006-05-01

Applicant: Kevin Beaman ,  John Moore ,  Ronald Weimer

Inventor： Kevin Beaman ,  John Moore ,  Ronald Weimer

IPC: H01L29/94 ,  H01L21/31

CPC classification number: H01L21/28185 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/3144 ,  H01L29/518 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of adjusting the threshold voltage of semiconductor devices by incorporating nitride into the isolation layer so as to decrease the mobility of charge carriers and thereby increase the threshold voltage required to activate the device. The nitrogen incorporation method may comprise of decoupled plasma nitridization (DPN) and the DPN can be performed in-situ during gate oxide formation. The amount of threshold voltage can be varied by adjusting the DPN treatment time and processing parameters.

公开(公告)号：US20060141698A1

公开(公告)日：2006-06-29

申请号：US11358524

申请日：2006-02-21

Applicant: Ronald Weimer

Inventor： Ronald Weimer

IPC: H01L21/20 ,  H01L21/8242

CPC classification number: H01L21/02332 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/84

Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon. The nitridized oxynitride layer inhibits oxidation of the underlying polysilicon layer in a post-treatment oxidizing anneal of the high K dielectric, thus maintaining the oxide layer as a thin layer over the polysilicon layer.

公开(公告)号：US20060115957A1

公开(公告)日：2006-06-01

申请号：US11327794

申请日：2006-01-06

Applicant: Cem Basceri ,  Trung Doan ,  Ronald Weimer ,  Kevin Beaman ,  Lyle Breiner ,  Lingyi Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David Kubista

Inventor： Cem Basceri ,  Trung Doan ,  Ronald Weimer ,  Kevin Beaman ,  Lyle Breiner ,  Lingyi Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David Kubista

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/302

CPC classification number: C23C16/45527 ,  C23C16/34 ,  C23C16/45546

Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

Abstract translation: 本公开提供了用于在批次的微特征工件上沉积材料中有用的方法和装置。 一个实施方案提供了一种方法，其中一定量的第一前体气体以第一封壳压力被引入外壳。 当以第一流速引入吹扫气体时，外壳内的压力降低到第二封闭压力。 第二外壳压力可接近或等于处理系统在第一流量下的稳态基础压力。 在降低压力之后，吹扫气体流量可以增加到第二流量，并且外壳压力可以增加到第三外壳压力。 此后，第二前体气体的流动可以在第四封闭压力下以外壳内的压力引入; 第三外壳压力理想地在第四外壳压力的约10％内。

公开(公告)号：US20050164466A1

公开(公告)日：2005-07-28

申请号：US10767298

申请日：2004-01-28

Applicant: Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  Cem Basceri ,  David Kubista

Inventor： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Kevin Beaman ,  Ronald Weimer ,  Cem Basceri ,  David Kubista

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/20

CPC classification number: H01L28/40 ,  H01L21/3141 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/84

Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50Å.

Abstract translation: 本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。 一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。 可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层 至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。 第二导电层可以与电介质层接触并具有不大于约50埃的厚度。

公开(公告)号：US20050059261A1

公开(公告)日：2005-03-17

申请号：US10665099

申请日：2003-09-17

Applicant: Cem Basceri ,  Trung Doan ,  Ronald Weimer ,  Kevin Beaman ,  Lyle Breiner ,  Lingyi Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David Kubista

Inventor： Cem Basceri ,  Trung Doan ,  Ronald Weimer ,  Kevin Beaman ,  Lyle Breiner ,  Lingyi Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David Kubista

IPC: C23C16/34 ,  H01L21/31

CPC classification number: C23C16/45527 ,  C23C16/34 ,  C23C16/45546

Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

Abstract translation: 本公开提供了用于在批次的微特征工件上沉积材料中有用的方法和装置。 一个实施方案提供了一种方法，其中一定量的第一前体气体以第一封壳压力被引入外壳。 当以第一流速引入吹扫气体时，外壳内的压力降低到第二封闭压力。 第二外壳压力可接近或等于处理系统在第一流量下的稳态基础压力。 在降低压力之后，吹扫气体流量可以增加到第二流量，并且外壳压力可以增加到第三外壳压力。 此后，第二前体气体的流动可以在第四封闭压力下以外壳内的压力引入; 第三外壳压力理想地在第四外壳压力的约10％内。

公开(公告)号：US20050048793A1

公开(公告)日：2005-03-03

申请号：US10640309

申请日：2003-08-14

Applicant: Ronald Weimer ,  Scott DeBoer ,  Dan Gealy ,  Husam Al-Shareef

Inventor： Ronald Weimer ,  Scott DeBoer ,  Dan Gealy ,  Husam Al-Shareef

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/469

CPC classification number: H01L21/3105 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/901

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract translation: 制造半导体器件的方法包括沉积电介质膜并使电介质膜在快速热处理室中进行湿氧化。 该技术可以用于例如在集成电路中形成各种元件，包括栅介质膜以及电容元件。 通过RTP工艺提供的紧密温度控制允许快速进行湿氧化，使得氧化物质不会通过电介质膜显着扩散并扩散到下层。 在电容元件的情况下，该技术还可以有助于降低电介质膜的漏电流，而不会显着降低其电容。