公开(公告)号：US5847995A

公开(公告)日：1998-12-08

申请号：US852354

申请日：1997-05-07

申请人： Shinichi Kobayashi ,  Shinji Kawai ,  Tadashi Omae ,  Makoto Oi ,  Akinori Matsuo ,  Masashi Wada ,  Kenji Kozakai

发明人： Shinichi Kobayashi ,  Shinji Kawai ,  Tadashi Omae ,  Makoto Oi ,  Akinori Matsuo ,  Masashi Wada ,  Kenji Kozakai

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/78

摘要： The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.

摘要翻译： 本发明的DINOR闪速存储器包括形成在多个电隔离P型阱上的多个块，备用块和备用字线块。 当在某个块中发生字线对阱短路并且选择另一个块时，导致字线对阱短路的块被带入非选择状态。 因此，在导致字线到阱短路的块中不发生泄漏，对所选择的块不会产生不良影响。

公开(公告)号：US5521417A

公开(公告)日：1996-05-28

申请号：US332377

申请日：1993-01-19

申请人： Masashi Wada

发明人： Masashi Wada

IPC分类号： H01L27/00 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11507 ,  H01L27/112 ,  H01L27/11293 ,  H01L27/11502

摘要： A semiconductor device with a non-volatile memory on a data processing block, having a semiconductor substrate (100); a data processing block (202) having active elements for performing data processing and formed directly on the semiconductor substrate (100); and a memory block (206, 302) for previously storing information necessary for performing the data processing. The passive memory cell array (302) is formed above the active data processing block (202) and the active peripheral circuit (206), with an insulating passivation film (110) interposed therebetween. The memory block includes a memory cell array (302) having a plurality of memory cells as passive elements and a peripheral circuit (206) having active elements for reading data from the memory cell array. The memory cell array (302) has a plurality of conductors (112) in the X direction and conductors (115) in the Y direction, respectively to be selected by the peripheral circuit (206). The X and Y direction conductors (112, 115) are formed as two upper and lower layers with an insulating film (113 ) interposed therebetween. The X and Y direction conductors are three-dimensionally intersected to form the memory cells.

摘要翻译： 一种在数据处理块上具有非易失性存储器的半导体器件，具有半导体衬底（100）; 具有用于执行数据处理并且直接形成在半导体衬底上的有源元件的数据处理块（202）; 以及用于预先存储执行数据处理所需的信息的存储块（206,302）。 无源存储单元阵列（302）形成在有源数据处理块（202）和有源外围电路（206）之上，绝缘钝化膜（110）插入其间。 存储块包括具有作为无源元件的多个存储单元的存储单元阵列（302）和具有用于从存储单元阵列读取数据的有源元件的外围电路（206）。 存储单元阵列（302）分别在X方向上具有多个导体（112），并且在Y方向上分别具有由外围电路（206）选择的导体（115）。 X和Y方向导体（112,115）形成为隔着绝缘膜（113）的两个上下层。 X和Y方向导体三维相交以形成存储单元。

公开(公告)号：US5262985A

公开(公告)日：1993-11-16

申请号：US659183

申请日：1991-02-22

申请人： Masashi Wada

发明人： Masashi Wada

IPC分类号： G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C16/00 ,  G11C16/06

CPC分类号： H01L27/11526 ,  G11C16/16 ,  H01L27/11546

摘要： A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array composed of a collection of blocks, each block containing memory cells sharing the source or drain, a first region having the memory cell array formed in its surface region, and a control circuit that, in the erase mode, sets the source shared by a plurality of memory cells to be erased in one block at a first potential and the first region at a second potential higher than the GND potential and lower than the first potential, and at the same time, sets the source shared by a plurality of memory cells not to be erased in other blocks at a third potential equal to or higher than the second potential and lower than the first potential.

公开(公告)号：US4990980A

公开(公告)日：1991-02-05

申请号：US390510

申请日：1989-08-07

申请人： Masashi Wada

发明人： Masashi Wada

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/06 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L29/0692 ,  H01L29/7827 ,  H01L29/945

摘要： Island layers defined by grooves are formed on a p.sup.+ -type silicon substrate. One memory cell having a MOS capacitor and a MOSFET transistor is formed in each island layer. The MOS capacitor is buried in a groove surrounding the island layer and has a capacitor electrode insulatively provided over the bottom surface of the groove and an n.sup.- -type semiconductor layer formed in a ring-shaped manner in the side surface region of the groove and facing the capacitor electrode. The MOSFET has a ring-shaped gate electrode for in the groove to be insulatively stacked over the capacitor electrode. The gate electrode faces a p-type channel region formed in a ring-shaped manner in the side surface region of the island layer. Only a drain layer is formed in the top surface region of the island layer.

摘要翻译： 由p +型硅衬底形成由沟槽限定的岛层。 在每个岛层形成具有MOS电容器和MOSFET晶体管的一个存储单元。 MOS电容器被埋在围绕岛层的沟槽中，并且具有绝缘地设置在沟槽的底表面上的电容器电极和在槽的侧表面区域以环状形成的n型半导体层， 面对电容器电极。 MOSFET具有用于凹槽中的环形栅电极，绝缘层叠在电容器电极上。 栅极电极面对在岛状层的侧面区域中以环状形成的p型沟道区域。 在岛层的顶面区域仅形成漏极层。

公开(公告)号：US08276263B2

公开(公告)日：2012-10-02

申请号：US12306701

申请日：2007-06-29

申请人： Masashi Wada ,  Hirotoshi Yamagata ,  Hiroyuki Takagi ,  Akira Kishida ,  Hiroaki Fujita

发明人： Masashi Wada ,  Hirotoshi Yamagata ,  Hiroyuki Takagi ,  Akira Kishida ,  Hiroaki Fujita

IPC分类号： H05K13/04

CPC分类号： H05K13/0452 ,  H05K13/0061 ,  H05K13/0853 ,  Y10T29/53174 ,  Y10T29/53187

摘要： A surface mounting apparatus includes a conveyer supporting a printed wiring board being moved in a transportation direction, and a board transfer device that lowers a pair of tab members to positions spaced apart upstream and downstream of the printed wiring board and moves the tab members in the transportation direction. The board transfer device includes an interval changing device to change an interval between a pair of the tab members and a sensor to detect the position of the printed wiring board, an interference determination means to determine the absence or presence of the printed wiring board at the positions to which both the tab members are to be lowered according to the position of the printed wiring board detected by the sensor and interval setting means to move the tab members by driving the interval changing device according to a detection result of the interference determination means.

摘要翻译： 一种表面安装装置，包括：支撑沿输送方向移动的印刷布线板的输送机;以及基板传送装置，其将一对突片部件降低到印刷布线板的上游和下游间隔开的位置，并使突片部件移动到 交通方向。 板传送装置包括间隔改变装置，用于改变一对突片构件之间的间隔和用于检测印刷布线板的位置的传感器;干涉确定装置，用于确定印刷电路板的不存在或不存在 根据由传感器检测的印刷电路板的位置和间隔设定装置，两个突片构件要被降下的位置，通过根据干扰判定装置的检测结果驱动间隔改变装置来移动突起构件。

公开(公告)号：US20110180708A1

公开(公告)日：2011-07-28

申请号：US13081875

申请日：2011-04-07

申请人： Katsunori Hirano ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

发明人： Katsunori Hirano ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

IPC分类号： H01J37/28

CPC分类号： G01N23/2251 ,  H01J2237/221 ,  H01J2237/2817

摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

摘要翻译： 用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。 用任意方向的电子束扫描样品中要测试的区域。 作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。 通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够执行高速扫描控制的具有多种扫描类型的测试装置。

公开(公告)号：US20100286415A1

公开(公告)日：2010-11-11

申请号：US12602013

申请日：2008-05-29

申请人： Yoshihiro Urade ,  Zhi-Li Huang ,  Masashi Wada ,  Nahoko Uchiyama ,  Tenji Konishi ,  Norio Nakamura

发明人： Yoshihiro Urade ,  Zhi-Li Huang ,  Masashi Wada ,  Nahoko Uchiyama ,  Tenji Konishi ,  Norio Nakamura

IPC分类号： C07D307/30

CPC分类号： C07D307/30 ,  A23L33/175

摘要： The invention provides a sleep-improving agent and a sedative agent containing, as an active ingredient, oxypinnatanine or its derivative represented by the following chemical formula (I):

摘要翻译： 本发明提供了含有以下化学式（I）表示的氧亚氨基酸或其衍生物作为活性成分的睡眠改善剂和镇静剂：

公开(公告)号：US20090277002A1

公开(公告)日：2009-11-12

申请号：US12306701

申请日：2007-06-29

申请人： Masashi Wada ,  Hirotoshi Yamagata ,  Hiroyuki Takagi ,  Akira Kishida ,  Hiroaki Fujita

发明人： Masashi Wada ,  Hirotoshi Yamagata ,  Hiroyuki Takagi ,  Akira Kishida ,  Hiroaki Fujita

IPC分类号： H05K13/04

CPC分类号： H05K13/0452 ,  H05K13/0061 ,  H05K13/0853 ,  Y10T29/53174 ,  Y10T29/53187

摘要： [Problems] To provide a surface mounting apparatus in which abutting members will not abut on a printed wiring board when the abutting members are lowered.[Means for Solving the Problems] A surface mounting apparatus includes a conveyer 34 or 53 that support a printed wiring board 2 movably in a transportation direction, and a board transfer device 14 that lowers a pair of tab members 71 and 71 to positions spaced apart upstream and downstream of the printed wiring board 2 in the transportation direction and moves the tab members 71 in the transportation direction. The board transfer device 14 includes an interval changing device that changes an interval between a pair of the tab members 71 and 71 and a sensor that detects the position of the printed wiring board 2 on the conveyer. The board transfer device 14 further includes interference determination means for determining the absence or presence of the printed wiring board 2 at the positions to which both the tab members 71 are to be lowered according to the position of the printed wiring board 2 detected by the sensor and interval setting means for moving the tab members 71 by driving the interval changing device according to a detection result of the interference determination means.

摘要翻译： [问题]提供一种表面安装装置，其中当抵接构件下降时，邻接构件不会抵接在印刷线路板上。 解决问题的手段表面安装装置包括：输送器34或53，其沿输送方向可移动地支撑印刷布线板2;以及板传送装置14，其将一对突片构件71和71降低到间隔开的位置 在输送方向上印刷布线板2的上游和下游，并沿着输送方向移动突出部件71。 板转移装置14包括间隔改变装置，其改变一对突片构件71和71之间的间隔以及检测印刷线路板2在输送机上的位置的传感器。 板转印装置14还包括干涉确定装置，用于根据由传感器检测到的印刷线路板2的位置来确定在两个突片部件71将被降低的位置处不存在或存在印刷线路板2 以及间隔设定装置，用于根据干扰确定装置的检测结果驱动间隔改变装置来移动突出部件71。

公开(公告)号：US06667928B2

公开(公告)日：2003-12-23

申请号：US10132248

申请日：2002-04-26

申请人： Kazuki Honma ,  Yoshiki Kawajiri ,  Masashi Wada ,  Mikio Sugawara ,  Hirofumi Sonoyama

发明人： Kazuki Honma ,  Yoshiki Kawajiri ,  Masashi Wada ,  Mikio Sugawara ,  Hirofumi Sonoyama

IPC分类号： G11C700

CPC分类号： G11C29/028 ,  G11C5/14 ,  G11C16/04 ,  G11C16/30 ,  G11C29/006 ,  G11C29/02 ,  G11C29/12005 ,  G11C2029/5004

摘要： Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management. The semiconductor chip includes a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of the first and second circuit blocks, with a first identification record indicative of the operability at the first voltage or a second identification record indicative of the operability only at the second voltage being held by the chip.

摘要翻译： 公开了一种独特增值的半导体芯片，提高产品的生产率和产量并促进生产管理的半导体集成电路器件，以及制造半导体集成电路器件的方法，其能够提高生产率和产量 产品和理性需求响应生产管理。 半导体芯片包括在第一电压和第二电压下操作的公共电路块，第二电压高于第一电压，被设计为适合第一电压并与公共电路块一致操作的第一电路块， 第二电路块，其被设计成适合第二电压并且与公共电路块一致地操作;以及电压类型建立电路，其激活第一和第二电路块中的一个，电压类型建立电路具有第一识别记录，其指示第一电压块的可操作性 电压或第二识别记录，仅指示在芯片所保持的第二电压下的可操作性。

公开(公告)号：US5544098A

公开(公告)日：1996-08-06

申请号：US455152

申请日：1995-05-31

申请人： Akinori Matsuo ,  Masashi Watanabe ,  Masashi Wada ,  Takeshi Wada ,  Yasuhiro Nakamura

发明人： Akinori Matsuo ,  Masashi Watanabe ,  Masashi Wada ,  Takeshi Wada ,  Yasuhiro Nakamura

IPC分类号： G06F12/16 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  G11C17/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/46 ,  G11C29/48 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/46 ,  G11C29/48

摘要： A semiconductor memory device having a plurality of nonvolatile memory devices or elements disposed in a matrix arrangement as one or more memory arrays is provided with a write operation and a verify mode which is automatically implemented when the write operation of the memory device ends. In connection with this, an auto-verify function is set in an internal circuit associated with the memory in accordance with a predetermined control signal and wherein a read mode subsequent to the write operation is implemented. During the auto-verify function, the read mode is implemented by effecting a data comparison circuit, such as an exclusive-OR logic circuit, which performs a coincidence/non-coincidence operation comparing the write data and the read data.