公开(公告)号：US20080305318A1

公开(公告)日：2008-12-11

申请号：US12163785

申请日：2008-06-27

申请人： Atsuo Ito ,  Yoshihiro Kubota ,  Kiyoshi Mitani

发明人： Atsuo Ito ,  Yoshihiro Kubota ,  Kiyoshi Mitani

IPC分类号： B32B27/32 ,  H01L21/30

CPC分类号： H01L21/76256 ,  C30B29/06 ,  C30B33/00 ,  H01L27/12

摘要： In a manufacturing method of manufacturing a silicon on insulator (SOI) wafer, a single crystal silicon whose surface is an N region on an outer side of an OSF region, is grown and sliced to fabricate an N region single crystal silicon. An ion injection layer is formed within the N region single crystal silicon wafer by injecting a hydrogen ion or a rare gas ion from a surface of the N region single crystal silicon wafer; the ion injection surface of the N region single crystal silicon wafer and/or a surface of the transparent insulation substrate is processed using plasma and/or ozone. The ion injection surface is bonded to the surface of the transparent insulation substrate by bringing them into close contact with each other at room temperature. An SOI layer is formed by mechanically peeling the single crystal silicon wafer.

摘要翻译： 在制造绝缘体上硅（SOI）晶片的制造方法中，生长表面为OSF区域外侧的N区的单晶硅，并切片以制造N区单晶硅。 通过从N区域单晶硅晶片的表面注入氢离子或稀有气体离子，在N区域单晶硅晶片内形成离子注入层; 使用等离子体和/或臭氧处理N区域单晶硅晶片的离子注入表面和/或透明绝缘衬底的表面。 离子注入表面通过在室温下彼此紧密接触而结合到透明绝缘基板的表面。 通过机械剥离单晶硅晶片形成SOI层。

公开(公告)号：US20070054459A1

公开(公告)日：2007-03-08

申请号：US11593009

申请日：2006-11-06

申请人： Hiroji Aga ,  Kiyoshi Mitani

发明人： Hiroji Aga ,  Kiyoshi Mitani

IPC分类号： H01L21/8222

CPC分类号： H01L21/76254

摘要： The present invention provides a SOI wafer produced by an ion implantation delamination method wherein a width of a SOI island region in a terrace portion generated in an edge portion of the SOI wafer where a surface of a base wafer is exposed is narrower than 1 mm and a density of pit-shaped defects having a size of 0.19 μm or more existing in a surface of a SOI layer detected by a LPD inspection is 1 counts/cm2 or less, and also provides a method for producing the SOI wafer. Thereby, there is provided a SOI wafer produced by an ion implantation delamination method wherein generation of SOI islands generated in delamination can be suppressed and a defect density of LPDs existing in a surface of the SOI wafer can be reduced, and a method for producing the same, so that device failure can be reduced.

摘要翻译： 本发明提供一种通过离子注入分层方法制造的SOI晶片，其中在SOI晶片的边缘部分中产生的露台部分中的SOI岛区域的宽度基底晶片暴露的距离窄于1mm， 存在于通过LPD检查检测的SOI层的表面中的具有0.19μm以上的尺寸的凹坑状缺陷的密度为1个/ cm 2以下，并且还提供了一种用于 生产SOI晶片。 因此，提供了通过离子注入分层方法制造的SOI晶片，其中可以抑制在分层中产生的SOI岛的产生，并且可以减少存在于SOI晶片的表面中的LPD的缺陷密度，以及制造 相同，从而可以减少设备故障。

公开(公告)号：US20050208322A1

公开(公告)日：2005-09-22

申请号：US11063867

申请日：2005-02-24

申请人： Thierry Barge ,  Bruno Ghyselen ,  Toshiaki Iwamatsu ,  Hideki Naruoka ,  Junichiro Furihata ,  Kiyoshi Mitani

发明人： Thierry Barge ,  Bruno Ghyselen ,  Toshiaki Iwamatsu ,  Hideki Naruoka ,  Junichiro Furihata ,  Kiyoshi Mitani

IPC分类号： H01L21/306 ,  H01L21/762 ,  G03C5/00 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/84 ,  H01L29/06 ,  H01L29/12 ,  H01L29/30

CPC分类号： H01L21/306 ,  H01L21/30625 ,  H01L21/76254 ,  Y10T428/12528

摘要： An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.

摘要翻译： 根据本发明的多层晶片的实施例包括基底基板，与基底基板相关联的第一层，以及在轴向方向上与基底基板相反一侧的第一层上的第二层，并且具有侧向边缘。 第一层包括沿着垂直于轴向方向测量的沿轴向突出并且横向邻近第二层布置的脊，用于保护侧边缘。 该脊可以围绕横向边缘围绕轴向横截面以防止边缘下降。 此外，脊可以具有大于第二层的轴向厚度的轴向高度。 在一个实施例中，第二层包括氧化半导体，第一层包括氧化绝缘体。

公开(公告)号：US06238990B1

公开(公告)日：2001-05-29

申请号：US09185901

申请日：1998-11-04

申请人： Hiroji Aga ,  Norihiro Kobayashi ,  Kiyoshi Mitani

发明人： Hiroji Aga ,  Norihiro Kobayashi ,  Kiyoshi Mitani

IPC分类号： H02L21336

CPC分类号： H01L21/3226 ,  H01L21/324 ,  H01L21/76256

摘要： A method for heat-treating an SOI wafer in a reducing atmosphere, wherein the SOI wafer is heat-treated through use of a rapid thermal annealer at a temperature within the range of 1100° C. to 1300° C. for 1 sec to 60 sec. The reducing atmosphere is preferably an atmosphere of 100% hydrogen or a mixed gas atmosphere containing hydrogen and argon. The heat treatment is preferably performed for 1 sec to 30 sec. The method eliminates COPs in an SOI layer of an SOI wafer in accordance with a hydrogen annealing method, while preventing etching of the SOI layer and a buried oxide layer.

摘要翻译： 一种用于在还原气氛中对SOI晶片进行热处理的方法，其中通过使用快速热退火炉在1100℃至1300℃的温度范围内对SOI晶片进行热处理1秒至60秒 秒 还原气氛优选为100％氢气或含有氢气和氩气的混合气体气氛。 优选进行1秒〜30秒的热处理。 该方法根据氢退火方法消除SOI晶片的SOI层中的COP，同时防止SOI层和掩埋氧化物层的蚀刻。

公开(公告)号：US5998281A

公开(公告)日：1999-12-07

申请号：US698457

申请日：1996-08-15

申请人： Hiroji Aga ,  Kiyoshi Mitani ,  Masatake Katayama

发明人： Hiroji Aga ,  Kiyoshi Mitani ,  Masatake Katayama

IPC分类号： H01L21/20 ,  H01L21/762

CPC分类号： H01L21/76251 ,  H01L21/2007 ,  Y10S148/012 ,  Y10S438/977

摘要： Proposed is an improvement in the process for the preparation of an SOI wafer comprising the steps of: forming an oxidized surface film on the mirror-polished surface of a first mirror-polished semiconductor silicon wafer as the base wafer; forming a doped layer with a dopant in a high concentration on the mirror-polished surface of a second mirror-polished semiconductor silicon wafer as the bond wafer; bringing the base wafer and the bond wafer into contact each with the other at the oxidized surface film and the doped layer; and subjecting the thus contacted semiconductor silicon wafers to a heat treatment to effect integral bonding thereof into a precursor of an SOI wafer. The improvement of the invention is accomplished by polishing the surface of the doped layer on the bond wafer before the base wafer and the bond wafer are joined by contacting at the oxidized surface film and the doped layer so that a great improvement can be obtained in the bonding strength between layers.

摘要翻译： 提出了制备SOI晶片的方法的改进，包括以下步骤：在作为基底晶片的第一镜面抛光半导体硅晶片的镜面抛光表面上形成氧化的表面膜; 在作为接合晶片的第二镜面抛光半导体硅晶片的镜面抛光表面上形成具有高浓度掺杂剂的掺杂层; 使基底晶片和接合晶片在氧化的表面膜和掺杂层处彼此接触; 以及对这样接触的半导体硅晶片进行热处理以使其整体结合到SOI晶片的前体中。 通过在基底晶片和接合晶片通过在氧化的表面膜和掺杂层之间接触而接合基底晶片和接合晶片之前，通过抛光接合晶片上的掺杂层的表面来实现本发明的改进，使得可以在 层之间的粘结强度。

公开(公告)号：US07608548B2

公开(公告)日：2009-10-27

申请号：US10570949

申请日：2004-09-07

申请人： Isao Yokokawa ,  Kiyoshi Mitani

发明人： Isao Yokokawa ,  Kiyoshi Mitani

IPC分类号： H01L21/302

CPC分类号： H01L21/02052 ,  H01L21/76254

摘要： Disclosed is a method for cleaning a multilayer substrate at least having a silicon single crystal wafer with a SiGe layer epitaxially grown on a surface of the silicon single crystal wafer, where the SiGe layer is an outermost surface of the SiGe layer and then cleaning the multilayer substrate with a first cleaning liquid capable of etching the protective film so that the protective film remains. The protective film prevents roughening of the surface of the SiGe layer while the cleaning is performed. The cleaning is performed. The cleaning is performed so that a thickness of the remaining protective film is from 1 nm to 100 nm.

摘要翻译： 公开了一种用于清洁至少具有硅单晶晶片的多层衬底的方法，所述硅单晶晶片在硅单晶晶片的表面上外延生长SiGe层，其中SiGe层是SiGe层的最外表面，然后清洗多层 基板，其具有能够蚀刻保护膜的第一清洁液体，使得保护膜保留。 在执行清洁时，保护膜防止SiGe层的表面的粗糙化。 进行清洁。 执行清洁，使得剩余保护膜的厚度为1nm至100nm。

公开(公告)号：US07550309B2

公开(公告)日：2009-06-23

申请号：US11662594

申请日：2005-09-16

申请人： Isao Yokokawa ,  Nobuhiko Noto ,  Kiyoshi Mitani

发明人： Isao Yokokawa ,  Nobuhiko Noto ,  Kiyoshi Mitani

IPC分类号： H01L21/00

CPC分类号： C30B33/06 ,  C30B29/30 ,  C30B29/32 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02694

摘要： The present invention is a method for producing a semiconductor wafer, comprising at least steps of, epitaxially growing a Si1-XGeX layer (0

摘要翻译： 本发明是一种制造半导体晶片的方法，至少包括以下步骤：在SOI晶片上外延生长Si1-XGeX层（0

公开(公告)号：US20080138959A1

公开(公告)日：2008-06-12

申请号：US11665977

申请日：2005-11-02

申请人： Isao Yokokawa ,  Hiroji Aga ,  Kiyoshi Mitani

发明人： Isao Yokokawa ,  Hiroji Aga ,  Kiyoshi Mitani

IPC分类号： H01L21/46

CPC分类号： H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/76254 ,  Y10S117/915

摘要： The present invention is a method for producing a semiconductor wafer, comprising: at least epitaxially growing a Si1-XGeX layer (0

摘要翻译： 本发明是一种用于制造半导体晶片的方法，其包括：至少外延生长Si 1-X 1 Ge x X 1层（0

公开(公告)号：US20060099791A1

公开(公告)日：2006-05-11

申请号：US11300503

申请日：2005-12-15

申请人： Kiyoshi Mitani ,  Kiyoshi Demizu ,  Isao Yokokawa ,  Tadahiro Ohmi ,  Shigetoshi Sugawa

发明人： Kiyoshi Mitani ,  Kiyoshi Demizu ,  Isao Yokokawa ,  Tadahiro Ohmi ,  Shigetoshi Sugawa

IPC分类号： H01L21/44

CPC分类号： H01L21/2007 ,  H01L21/76254 ,  H01L29/045

摘要： The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal plane orientation of {100}. The present invention also provides a method of producing a bonded wafer, wherein after at least a first silicon single crystal wafer having a crystal plane orientation of {110} and a second silicon single crystal wafer having a crystal plane orientation of {100} are bonded directly or bonded via an insulator film, the first silicon single crystal wafer is made into a thin film. Thereby, there can be provided a wafer possible to obtain a MIS device having good characteristics by utilizing a silicon single crystal wafer having the {110} plane.

公开(公告)号：US20060040469A1

公开(公告)日：2006-02-23

申请号：US10522413

申请日：2003-07-16

申请人： Hiroji Aga ,  Kiyoshi Mitani

发明人： Hiroji Aga ,  Kiyoshi Mitani

IPC分类号： H01L21/30 ,  H01L21/425

CPC分类号： H01L21/265 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/76254

摘要： In order to adjust thickness of a bonded silicon single crystal film 15 depending of thickness of an SOI layer 5 to be obtained, depth of formation d1+tx of a separatory ion implanted layer 4, measured from a first main surface J, in the separatory ion implanted layer formation step is adjusted through energy of the ion implantation. Dose of the ion implantation is set smaller as the depth of formation measured from the first main surface J becomes smaller. A smaller dose results in a smaller surface roughness of the separation surface, and makes it possible to reduce polishing stock removal of the separation surface of the bonded silicon single crystal film in the planarization step. Uniformity in the thickness of the SOI layer can consequently be improved even for the case where a thin SOI layer has to be formed. The present invention is therefore successful in providing a method of fabricating an SOI wafer capable of suppressing variations in the intra-wafer and inter-wafer uniformity of the thickness of the SOI layer to a sufficiently low level, even for the case where a required level of the thickness of the SOI layer is extremely small.

摘要翻译： 为了根据所获得的SOI层5的厚度来调整键合硅单晶膜15的厚度，从第一主表面J测量的分离离子注入层4的形成深度d 1 + t x， 通过离子注入的能量来调节分离离子注入层形成步骤。 随着从第一主表面J测量的深度变小，离子注入的剂量变小。 较小的剂量导致分离表面的较小的表面粗糙度，并且使得可以在平坦化步骤中减少接合的硅单晶膜的分离表面的抛光原料去除。 因此，即使在必须形成薄的SOI层的情况下，也可以提高SOI层的厚度的均匀性。 因此，本发明成功地提供了一种制造SOI晶片的方法，其能够将SOI层的厚度的晶片内和晶片间均匀度的均匀度抑制到足够低的水平，即使在要求的水平的情况下 的SOI层的厚度非常小。