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公开(公告)号：US20140124871A1
公开(公告)日：2014-05-08
申请号：US14161611
申请日：2014-01-22
Applicant: MEDIATEK INC.
Inventor： Ching-Chung Ko , Tung-Hsing Lee
IPC: H01L27/06
CPC classification number: H01L27/0623 , H01L21/8249 , H01L29/0649 , H01L29/0692 , H01L29/0821 , H01L29/6625 , H01L29/735
Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.
Abstract translation: 横向双极结晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 以及围绕所述基底区域的收集器区域; 其中所述栅极下方的所述基极区域的所述部分未经过阈值电压注入工艺。
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公开(公告)号：US20250148271A1
公开(公告)日：2025-05-08
申请号：US18915358
申请日：2024-10-15
Applicant: MEDIATEK INC.
Inventor： Yu-Lin Yang , Po-Chao Tsao , Hsiang-An Chen , Chin-Wei Lin , Ming-Cheng Lee , Tung-Hsing Lee
IPC: G06N3/0475
Abstract: An adaptive minimum voltage aging margin prediction method includes acquiring characteristic data of a plurality of dies in a testing line, predicting a wear-out failure rate of each module of the plurality of dies according to the characteristic data by using a neural network, and predicting a minimum voltage aging margin of the each module according to the wear-out failure rate of the each module by using the neural network.
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13.发明公开公开(公告)号：US20240230755A9
公开(公告)日：2024-07-11
申请号：US18376447
申请日：2023-10-04
Applicant: MEDIATEK INC.
Inventor： Yu-Lin Yang , Chin-Wei Lin , Po-Chao Tsao , Tung-Hsing Lee , Chia-Jung Ni , Chi-Ming Lee , Yi-Ju Ting
CPC classification number: G01R31/2894 , G06N20/00
Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.
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公开(公告)号：US09786560B2
公开(公告)日：2017-10-10
申请号：US15365435
申请日：2016-11-30
Applicant: MediaTek Inc.
Inventor： Cheng-Chou Hung , Ming-Tzong Yang , Tung-Hsing Lee , Wei-Che Huang , Yu-Hua Huang , Tzu-Hung Lin
IPC: H01L23/48 , H01L21/768 , H01L29/06 , H01L21/761 , H01L23/00 , H01L23/498
CPC classification number: H01L21/76898 , H01L21/761 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L24/11 , H01L29/0619 , H01L29/0623 , H01L2224/13 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.
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公开(公告)号：US09543232B2
公开(公告)日：2017-01-10
申请号：US14601440
申请日：2015-01-21
Applicant: MediaTek Inc.
Inventor： Cheng-Chou Hung , Ming-Tzong Yang , Tung-Hsing Lee , Wei-Che Huang , Yu-Hua Huang , Tzu-Hung Lin
IPC: H01L23/48 , H01L29/06 , H01L21/761 , H01L21/768
CPC classification number: H01L21/76898 , H01L21/761 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L24/11 , H01L29/0619 , H01L29/0623 , H01L2224/13 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a front side and a back side. The semiconductor package structure includes a through silicon via (TSV) interconnect structure formed in the substrate; and a first guard ring doped region and a second guard ring doped region formed in the substrate, and the first guard ring doped region and the second guard ring doped region are adjacent to the TSV interconnect structure.
Abstract translation: 提供一种半导体封装结构及其形成方法。 半导体封装结构包括衬底，并且衬底具有正面和背面。 半导体封装结构包括在衬底中形成的穿硅通孔（TSV）互连结构; 以及形成在所述衬底中的第一保护环掺杂区域和第二保护环掺杂区域，并且所述第一保护环掺杂区域和所述第二保护环掺杂区域与所述TSV互连结构相邻。
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Patent Agency Ranking
公开(公告)号：US09425098B2
公开(公告)日：2016-08-23
申请号：US14621703
申请日：2015-02-13
Applicant: MediaTek Inc.
Inventor： Ming-Tzong Yang , Cheng-Chou Hung , Tung-Hsing Lee , Wei-Che Huang , Yu-Hua Huang
IPC: H01L23/00 , H01L21/768 , H01L21/268 , H01L21/306 , H01L23/522 , H01L31/18 , H01L23/48 , H01L21/02 , H01L23/66
CPC classification number: H01L21/76898 , H01L21/02107 , H01L21/268 , H01L21/30625 , H01L23/481 , H01L23/5227 , H01L23/66 , H01L24/11 , H01L24/13 , H01L24/16 , H01L31/18 , H01L2223/6616 , H01L2224/13025 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/11 , H01L2924/12042 , H01L2924/014 , H01L2924/00014 , H01L2924/00
Abstract: A method for fabricating a electronic device package provides a electronic device chip, wherein the electronic device chip includes a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate has a first thickness, an electronic component disposed on the front side of the semiconductor substrate, and an interconnect structure disposed on the electronic component. The method further performs a thinning process to remove a portion of the semiconductor substrate from the back side thereof. The method then removes a portion of the thinned semiconductor substrate and a portion of a dielectric layer of the interconnect structure from a back side of the thinned semiconductor substrate until a first metal layer pattern of the interconnect structure is exposed, thereby forming a through hole. Finally, the method forms a TSV structure in the through hole, and mounts the electronic device chip on a base.
Abstract translation: 一种制造电子器件封装的方法，提供了一种电子器件芯片，其中电子器件芯片包括具有正面和背面的半导体衬底，其中半导体衬底具有第一厚度，电子部件设置在第一厚度的前侧 半导体衬底和布置在电子部件上的互连结构。 该方法还进行薄膜化处理以从其背面去除半导体衬底的一部分。 然后，该方法从减薄的半导体衬底的背面去除一部分减薄的半导体衬底和互连结构的电介质层的一部分，直到互连结构的第一金属层图案被暴露，从而形成通孔。 最后，该方法在通孔中形成TSV结构，并将电子设备芯片安装在基座上。
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公开(公告)号：US20150364549A1
公开(公告)日：2015-12-17
申请号：US14301348
申请日：2014-06-11
Applicant: MEDIATEK INC.
Inventor： Tung-Hsing Lee , Ming-Tzong Yang , Wei-Che Huang , Cheng-Chou Hung
CPC classification number: H01L29/1608 , H01L29/0653 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
Abstract: A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiC device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiC.
Abstract translation: 具有用于减轻微负载效应的虚设图形的半导体器件包括其内部区域和外部区域之间具有中间环形区域的半导体衬底; 在所述内部区域中的所述半导体衬底上的SiC器件; 以及设置在中间环形区域内的半导体衬底上的多个虚设图案。 至少一个虚拟图案包含SiC。
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公开(公告)号：US09190976B2
公开(公告)日：2015-11-17
申请号：US13804206
申请日：2013-03-14
Applicant: MediaTek Inc.
Inventor： Ming-Tzong Yang , Cheng-Chou Hung , Tung-Hsing Lee , Wei-Che Huang
CPC classification number: H03H7/0115 , H01P1/20381 , H01P7/082 , H03H3/00
Abstract: An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators.
Abstract translation: 本发明的实施例提供一种无源器件单元。 无源器件单元具有衬底层，无源器件以及形成在衬底层和无源器件之间的中间层。 中间层包括多个LC谐振器。
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公开(公告)号：US20140127869A1
公开(公告)日：2014-05-08
申请号：US14161570
申请日：2014-01-22
Applicant: MEDIATEK INC.
Inventor： Ching-Chung Ko , Tung-Hsing Lee
IPC: H01L21/8249
CPC classification number: H01L27/0623 , H01L21/8249 , H01L29/0649 , H01L29/0692 , H01L29/0821 , H01L29/6625 , H01L29/735
Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.
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公开(公告)号：US20130265121A1
公开(公告)日：2013-10-10
申请号：US13804206
申请日：2013-03-14
Applicant: MEDIATEK INC.
Inventor： Ming-Tzong YANG , Cheng-Chou Hung , Tung-Hsing Lee , Wei-Che Huang
CPC classification number: H03H7/0115 , H01P1/20381 , H01P7/082 , H03H3/00
Abstract: An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators.
Abstract translation: 本发明的实施例提供一种无源器件单元。 无源器件单元具有衬底层，无源器件和形成在衬底层和无源器件之间的中间层。 中间层包括多个LC谐振器。
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