公开(公告)号：US08970416B2

公开(公告)日：2015-03-03

申请号：US14202823

申请日：2014-03-10

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix

IPC: H03M3/00 ,  H03M1/80 ,  H03M1/06

CPC classification number: H03M1/802 ,  H03M1/0665 ,  H03M3/30 ,  H03M3/424 ,  H03M3/464

Abstract: A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+1 output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.

Abstract translation: 一种用于Σ-Δ调制器的电荷转移型数模转换器（DAC）包括一个可操作以产生4n + 1输出电平的电容器开关单元，包括：多个第二开关单元，用于将第 具有正或负参考信号的多个参考电容器对; 其中所述多个参考电容器对中的第二端子分别并联耦合; 其中，对于偶数传输，提供单个切换组合以实现线性，并且其中对于奇数传输，提供不同切换组合的平均值以实现线性度; 其中偶数传输是当DAC的输入是偶数时，并且奇数传输是当DAC的输入是奇数时。

公开(公告)号：US20130120032A1

公开(公告)日：2013-05-16

申请号：US13671903

申请日：2012-11-08

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix

IPC: H03L7/00 ,  H03L7/06

CPC classification number: H03M1/10 ,  G06F13/423 ,  G06F13/4282 ,  H03L7/00 ,  H03L7/06

Abstract: An analog front end (AFE) device has at least one programmable analog-to-digital converter (ADC) and a serial interface switchable to operate in a bidirectional serial interface mode and in a unidirectional two wire serial interface mode, wherein the unidirectional two wire serial interface mode only uses a clock input and a data output signal line, wherein the ADC operates in the unidirectional two wire serial interface mode synchronous with a clock supplied to the clock input.

Abstract translation: 模拟前端（AFE）装置具有至少一个可编程模数转换器（ADC）和可转换成双向串行接口模式和单向双线串行接口模式的串行接口，其中单向两线 串行接口模式仅使用时钟输入和数据输出信号线，其中ADC以提供给时钟输入的时钟同步的单向两线串行接口模式工作。

公开(公告)号：US11386025B2

公开(公告)日：2022-07-12

申请号：US16998170

申请日：2020-08-20

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix ,  Yann Johner

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/42

Abstract: An apparatus may include a serial data output port configured to send output data to a electronic device. The apparatus may include a serial data input port configured to receive input data from another electronic device. The apparatus may include a chip select output port configured to send output to the electronic devices connected in a daisy chain. The apparatus may include a interface circuit, configured to determine that a given electronic device is to selectively execute a first command. The interface circuit may be further configured to issue a complex command to the electronic devices connected. The complex command may indicate to the f electronic devices that additional commands are to be selectively executed.

公开(公告)号：US11057048B2

公开(公告)日：2021-07-06

申请号：US16879941

申请日：2020-05-21

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix

IPC: H03M3/00 ,  H03M1/12

Abstract: An analog to digital converter (ADC) includes voltage and reference input terminals, a buffer circuit, and control logic. The buffer circuit includes input and output terminals and a variable resistor including resistive branches connected in parallel. The control logic is configured to, in a calibration phase, determine a given gain value for which gain error is to be calibrated, determine a set of the resistive branches in the buffer circuit to be used to achieve the given gain value, successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled, determine an output code resulting after enabling all resistive branches of the set, and, from the output code, determine a gain error of the given gain value. The control logic is further configured to take corrective action based upon the gain error of the given gain value.

公开(公告)号：US11057047B2

公开(公告)日：2021-07-06

申请号：US16879917

申请日：2020-05-21

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix ,  Zeynep Sueda Turk

IPC: H03M1/46 ,  H03M1/12 ,  H03M1/10

Abstract: An analog to digital converter (ADC) circuit includes voltage and reference input terminals, a sample circuit, and control logic. The sample circuit includes input and output terminals, and capacitors connected in parallel and arranged between the input and output terminals. The control logic is configured to, in a calibration phase of operation, cause the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal, determine a given gain value, determine a set of the capacitors to be used to achieve the given gain value, successively enable capacitor subsets to sample voltage of the reference input while disabling a remainder of the capacitors until all capacitors have been enabled, determine a resulting output code, and from the output code, determine a gain error of the given gain value of the ADC circuit.

公开(公告)号：US20190334545A1

公开(公告)日：2019-10-31

申请号：US16394392

申请日：2019-04-25

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix ,  Eve Carletti

IPC: H03M3/00

Abstract: A method includes receiving samples of digital to analog converter (DAC), partitioning the samples to unit-DACs based upon previous partitions of inputs to the unit-DACs to cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs, including partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm. The algorithm includes, for each DAC input, determining a first partition of the DAC input that would cancel an (n−1)th order previously integrated non-linearity, adding an equivalent DAC input of the first partition to the DAC input to obtain a total DAC input, using a first order application of the total DAC input to the inputs of the unit-DACs to yield a second partition of DAC input, summing the first and second partitions generate a final partition, and, based on the final partition, computing non-linearity remainders at each order of integration.

公开(公告)号：US20160204794A1

公开(公告)日：2016-07-14

申请号：US14594388

申请日：2015-01-12

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix

IPC: H03M3/00 ,  H03M1/66 ,  H03M1/06

CPC classification number: H03M3/33 ,  H03M1/0641 ,  H03M1/361 ,  H03M1/66 ,  H03M3/424

Abstract: A sigma-delta analog to digital converter (ADC) includes an M-bit digital-to-analog converter (DAC); a loop filter coupled to receive an output from DAC; and a variable level quantizer configured to provide a uniform quantization function by switching between an N-level quantizer function and an N-1 level quantizer function

Abstract translation: Σ-Δ模数转换器（ADC）包括M位数模转换器（DAC）; 耦合以接收DAC的输出的环路滤波器; 以及可变电平量化器，被配置为通过在N电平量化器功能和N-1电平量化器功能之间切换来提供均匀的量化功能

公开(公告)号：US20190097609A1

公开(公告)日：2019-03-28

申请号：US16138156

申请日：2018-09-21

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix ,  Fabien Vaucher

IPC: H03H19/00 ,  H03M1/80 ,  H03M1/06 ,  H03M3/00

Abstract: A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.

公开(公告)号：US10197605B2

公开(公告)日：2019-02-05

申请号：US14669232

申请日：2015-03-26

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix ,  Michael Brumann

IPC: G01R21/00 ,  G01R21/06 ,  G01R21/133 ,  G01R23/165 ,  H03L7/099 ,  H03M1/12 ,  H03M1/36

Abstract: A power metering circuit includes a current input path for receiving an analog current input at a first analog to digital converter; a voltage input path for receiving an analog voltage input at a second analog to digital converter; a multiplier configured to multiply an output of the current input path and the voltage input path; a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency.

公开(公告)号：US20160336953A1

公开(公告)日：2016-11-17

申请号：US14710105

申请日：2015-05-12

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix ,  Alexandre Barreto

IPC: H03M1/34 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/34 ,  G06F1/3203 ,  G06F1/325 ,  G06F3/05 ,  H03M1/001 ,  H03M1/002 ,  H03M1/12 ,  H03M1/1245

Abstract: An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time

Abstract translation: 模数转换器包括用于接收模拟输入并将输入转换成数字信号的电路; 以及非瞬态控制电路，被配置为：接收采样时间; 接收转换时间; 从至少一个睡眠模式确定上电时间; 并且如果上电时间和转换时间的总和小于采样时间，则使数模转换器进入至少一个休眠模式