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公开(公告)号：US20190056989A1
公开(公告)日：2019-02-21
申请号：US15677736
申请日：2017-08-15
Applicant: Micron Technology, Inc.
Inventor： Dheeraj Srinivasan , Ali Mohammadzadeh
CPC classification number: G06F11/1012 , G06F11/1068 , G11C8/12 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/102 , G11C16/28 , G11C29/021 , G11C29/028 , G11C2211/5634 , G11C2211/5641 , H03M13/37
Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.
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公开(公告)号：US10120604B1
公开(公告)日：2018-11-06
申请号：US15621448
申请日：2017-06-13
Applicant: Micron Technology, Inc.
Inventor： Dheeraj Srinivasan , Ali Mohammadzadeh
IPC: G06F3/06 , G06F12/0811 , G11C11/56 , G11C16/10
Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states, and a second of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular second one of the target states.
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公开(公告)号：US09875802B2
公开(公告)日：2018-01-23
申请号：US15342255
申请日：2016-11-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
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公开(公告)号：US09218884B2
公开(公告)日：2015-12-22
申请号：US14153590
申请日：2014-01-13
Applicant: Micron Technology, Inc.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
Abstract translation: 公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。
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公开(公告)号：US12282669B2
公开(公告)日：2025-04-22
申请号：US18621747
申请日：2024-03-29
Applicant: Micron Technology, Inc.
Inventor： Luca Nubile , Walter Di Francesco , Fumin Gu , Ali Mohammadzadeh , Biagio Iorio , Liang Yu
IPC: G06F3/06
Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.
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Patent Agency Ranking
公开(公告)号：US12094547B2
公开(公告)日：2024-09-17
申请号：US17893364
申请日：2022-08-23
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Ali Mohammadzadeh , Walter Di Francesco , Dheeraj Srinivasan
CPC classification number: G11C16/3459 , G11C7/1039 , G11C16/102 , G11C16/26
Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.
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公开(公告)号：US20230060312A1
公开(公告)日：2023-03-02
申请号：US17893364
申请日：2022-08-23
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Ali Mohammadzadeh , Walter Di Francesco , Dheeraj Srinivasan
Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.
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公开(公告)号：US20230043418A1
公开(公告)日：2023-02-09
申请号：US17514267
申请日：2021-10-29
Applicant: Micron Technology, Inc.
Inventor： Karl D. Schuh , Ali Mohammadzadeh , Dheeraj Srinivasan , Daniel J. Hubbard , Luca Bert
IPC: G06F3/06
Abstract: Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.
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公开(公告)号：US11264099B2
公开(公告)日：2022-03-01
申请号：US17090067
申请日：2020-11-05
Applicant: Micron Technology, Inc.
Inventor： Dheeraj Srinivasan , Jeffrey M. Tsai , Ali Mohammadzadeh , Terry M. Grunzke
Abstract: An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.
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公开(公告)号：US20220011959A1
公开(公告)日：2022-01-13
申请号：US16946869
申请日：2020-07-09
Applicant: Micron Technology, Inc.
Inventor： Dheeraj Srinivasan , Ali Mohammadzadeh
Abstract: A processing device in a memory sub-system determines whether to check a status of one or more memory dies of the memory device and sends a multi-unit status command to the memory device, the multi-unit status command specifying a plurality of memory units associated with the one or more memory dies of the memory device. The processing device further receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.
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