公开(公告)号：US10069069B2

公开(公告)日：2018-09-04

申请号：US15848477

申请日：2017-12-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Swapnil A. Lengade ,  John M. Meldrim ,  Andrea Gotti

IPC: H01L45/00 ,  H01L27/24

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, a second electrode portion is coupled to the second chalcogenide structure, and a third electrode portion is between the first and second electrode portions. A first portion of an electrically conductive barrier material is disposed between the first and third electrode portions. A second portion of the electrically conductive barrier material is disposed between the second and third electrode portions.

公开(公告)号：US09634245B2

公开(公告)日：2017-04-25

申请号：US14594038

申请日：2015-01-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Innocenzo Tortorelli ,  Enrico Varesi

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L45/06 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements.

公开(公告)号：US20150349249A1

公开(公告)日：2015-12-03

申请号：US14824128

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Davide Colombo

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/12 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608

Abstract: Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described.

Abstract translation: 具有位于第一电极和第二电极之间的选择器件材料的存储器单元，位于第二电极和第三电极之间的存储元件以及位于存储元件的第一部分和第二电极之间的多个导电扩散阻挡材料 存储元件的一部分。 具有选择装置的存储单元包括位于第一电极和第二电极之间的选择装置材料，位于第二电极和第三电极之间的存储元件以及位于选择器的第一部分之间的多个导电扩散阻挡材料 设备和选择设备的第二部分。 还描述了制造方法。

公开(公告)号：US20150263281A1

公开(公告)日：2015-09-17

申请号：US14727106

申请日：2015-06-01

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  Luca Fumagalli

IPC: H01L45/00

CPC classification number: H01L45/1293 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625

Abstract: A phase change memory cell comprising a first chalcogenide compound on a first electrode, a first nitrogenated carbon material directly on the first chalcogenide compound, a second chalcogenide compound directly on the first nitrogenated carbon material, and a second nitrogenated carbon material directly on the second chalcogenide compound and directly on a second electrode. Other phase change memory cells are described. A method of forming a phase change memory cell and a phase change memory device are also described.

Abstract translation: 一种相变存储单元，包括在第一电极上的第一硫族化合物，直接位于第一硫属化物化合物上的第一含氮碳材料，直接位于第一氮化碳材料上的第二硫族化合物，以及直接位于第二硫族化物上的第二含氮碳材料 化合物并直接在第二电极上。 其他相变存储单元被描述。 还描述了形成相变存储单元和相变存储器件的方法。

公开(公告)号：US20150028284A1

公开(公告)日：2015-01-29

申请号：US13952162

申请日：2013-07-26

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Davide Columbo

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/12 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608

Abstract: Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described.

公开(公告)号：US20220376176A1

公开(公告)日：2022-11-24

申请号：US17818313

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00 ,  H01L27/24

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US11444243B2

公开(公告)日：2022-09-13

申请号：US16665679

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US11094879B2

公开(公告)日：2021-08-17

申请号：US16121261

申请日：2018-09-04

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Innocenzo Tortorelli ,  Enrico Varesi

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/22

Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements.

公开(公告)号：US20210234097A1

公开(公告)日：2021-07-29

申请号：US17165549

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  Pavan Reddy K. Aella ,  Dale W. Collins

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

公开(公告)号：US11038107B2

公开(公告)日：2021-06-15

申请号：US16202379

申请日：2018-11-28

Applicant: Micron Technology, Inc.

Inventor： Dale W. Collins ,  Andrea Gotti ,  F. Daniel Gealy ,  Tuman E. Allen ,  Swapnil Lengade

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.