公开(公告)号：US20160365514A1

公开(公告)日：2016-12-15

申请号：US15244629

申请日：2016-08-23

Applicant: Micron Technology, Inc.

Inventor： Zhe Song ,  Tuman E. Allen ,  Cole S. Franklin ,  F. Daniel Gealy

IPC: H01L45/00 ,  H01L27/115 ,  H01L27/24

Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

公开(公告)号：US20130258550A1

公开(公告)日：2013-10-03

申请号：US13903364

申请日：2013-05-28

Applicant: Micron Technology, Inc.

Inventor： Rishikesh Krishnan ,  F. Daniel Gealy ,  Vidya Srividya ,  Noel Rocklein

IPC: H01G4/255

CPC classification number: H01G4/255 ,  H01L27/10852 ,  H01L28/65

Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.

公开(公告)号：US09634245B2

公开(公告)日：2017-04-25

申请号：US14594038

申请日：2015-01-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Innocenzo Tortorelli ,  Enrico Varesi

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L45/06 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements.

公开(公告)号：US09627501B2

公开(公告)日：2017-04-18

申请号：US14607733

申请日：2015-01-28

Applicant: Micron Technology, Inc.

Inventor： F. Daniel Gealy ,  Vishwanath Bhat ,  Cancheepuram V. Srividya ,  M. Noel Rocklein

IPC: H01L29/51 ,  H01L49/02 ,  H01L29/78 ,  C23C16/455 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316

CPC classification number: H01L21/022 ,  C23C16/45529 ,  H01L21/02148 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/40 ,  H01L28/56 ,  H01L29/517 ,  H01L29/78

Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

公开(公告)号：US20160013360A1

公开(公告)日：2016-01-14

申请号：US14866241

申请日：2015-09-25

Applicant: Micron Technology, Inc.

Inventor： Belford T. Coursey ,  F. Daniel Gealy ,  George E. Beck

IPC: H01L33/00 ,  H01L33/32 ,  H01L21/762 ,  H01L33/06

CPC classification number: H01L33/0079 ,  H01L21/76254 ,  H01L33/007 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32

Abstract: Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a shear strength enhancement material at a front surface of a donor substrate and implanting ions a depth into the donor substrate through the shear strength enhancement material. The ion implantation can form a doped portion in the donor substrate that defines an epitaxial formation structure. The method can further include transferring the epitaxial formation structure from the donor substrate to a front surface of a handle substrate. The shear strength enhancement material can be positioned between the epitaxial formation structure and the front surface of the handle substrate and bridge defects in the front surface of the handle substrate.

Abstract translation: 本文公开了具有增强的剪切强度的外延形成结构和相关系统和方法的工程衬底。 在几个实施例中，例如，可以通过在施主衬底的前表面处形成剪切强度增强材料并通过剪切强度增强材料将离子深度注入到施主衬底中来制造工程衬底。 离子注入可以在施主衬底中形成限定外延形成结构的掺杂部分。 该方法还可以包括将外延形成结构从施主衬底转移到手柄衬底的前表面。 剪切强度增强材料可以位于外延形成结构和手柄基板的前表面之间并且在手柄基板的前表面中桥接缺陷。

公开(公告)号：US20150349249A1

公开(公告)日：2015-12-03

申请号：US14824128

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Davide Colombo

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/12 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608

Abstract: Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described.

Abstract translation: 具有位于第一电极和第二电极之间的选择器件材料的存储器单元，位于第二电极和第三电极之间的存储元件以及位于存储元件的第一部分和第二电极之间的多个导电扩散阻挡材料 存储元件的一部分。 具有选择装置的存储单元包括位于第一电极和第二电极之间的选择装置材料，位于第二电极和第三电极之间的存储元件以及位于选择器的第一部分之间的多个导电扩散阻挡材料 设备和选择设备的第二部分。 还描述了制造方法。

公开(公告)号：US20150247236A1

公开(公告)日：2015-09-03

申请号：US14699830

申请日：2015-04-29

Applicant: Micron Technology, Inc.

Inventor： Ross S. Dando ,  F. Daniel Gealy

IPC: C23C16/04 ,  C23C16/455 ,  C23C16/48 ,  C23C16/52

CPC classification number: C23C16/047 ,  C23C16/45525 ,  C23C16/483 ,  C23C16/52

Abstract: Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces are disclosed herein. In one embodiment, a method includes depositing molecules of a gas onto a microfeature workpiece in the reaction chamber and selectively irradiating a first portion of the molecules on the microfeature workpiece in the reaction chamber with a selected radiation without irradiating a second portion of the molecules on the workpiece with the selected radiation. The first portion of the molecules can be irradiated to activate the portion of the molecules or desorb the portion of the molecules from the workpiece. The first portion of the molecules can be selectively irradiated by impinging the first portion of the molecules with a laser beam or other energy source.

Abstract translation: 本文公开了在反应室中的微型工件上沉积材料的方法和用于将材料沉积到微特征工件上的系统。 在一个实施方案中，一种方法包括将气体的分子沉积到反应室中的微特征工件上，并用选定的辐射选择性地照射反应室中的微特征工件上的分子的第一部分，而不会将分子的第二部分 工件与选定的辐射。 可以照射分子的第一部分以激活分子的一部分或从工件解吸部分分子。 分子的第一部分可以通过用激光束或其他能量源撞击分子的第一部分来选择性地照射。

公开(公告)号：US20150137254A1

公开(公告)日：2015-05-21

申请号：US14607733

申请日：2015-01-28

Applicant: Micron Technology, Inc.

Inventor： F. Daniel Gealy ,  Vishwanath Bhat ,  Cancheepuram V. Srividya ,  M. Noel Rocklein

IPC: H01L29/51 ,  H01L49/02

CPC classification number: H01L21/022 ,  C23C16/45529 ,  H01L21/02148 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/40 ,  H01L28/56 ,  H01L29/517 ,  H01L29/78

Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

Abstract translation: 梯度介电层和制造这种电介质层的方法在各种电子结构中提供电介质以用于广泛的电子设备和系统。 在一个实施例中，电介质层相对于跨介电层的掺杂分布而分级。 在一个实施例中，电介质层相对于介电层上的晶体结构分布呈梯度分布。 在一个实施例中，通过包含测序技术的原子层沉积形成电介质层以产生掺杂的电介质材料。

公开(公告)号：US20150028284A1

公开(公告)日：2015-01-29

申请号：US13952162

申请日：2013-07-26

Applicant: Micron Technology, Inc.

Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Davide Columbo

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/12 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608

Abstract: Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described.

公开(公告)号：US20190097133A1

公开(公告)日：2019-03-28

申请号：US16202379

申请日：2018-11-28

Applicant: Micron Technology, Inc.

Inventor： Dale W. Collins ,  Andrea Gotti ,  F. Daniel Gealy ,  Tuman E. Allen ,  Swapnil Lengade

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.