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    PACKAGE COOLING BY COIL CAVITY
    11.
    发明申请
    PACKAGE COOLING BY COIL CAVITY 审中-公开

    公开(公告)号：US20200211916A1

    公开(公告)日：2020-07-02

    申请号：US16237111

    申请日：2018-12-31

    Applicant: Micron Technology, Inc.

    Inventor： Andrew M. Bayless ,  Wayne H. Huang ,  Owen R. Fay

    IPC: H01L23/31 ,  H01L23/473 ,  H01L23/467 ,  H01L23/36 ,  H01L21/56

    Abstract: A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid.

    Semiconductor devices with recessed pads for die stack interconnections
    15.
    发明授权
    Semiconductor devices with recessed pads for die stack interconnections 有权

    公开(公告)号：US11715696B2

    公开(公告)日：2023-08-01

    申请号：US17237496

    申请日：2021-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Ruei Ying Sheng ,  Andrew M. Bayless ,  Brandon P. Wirz

    IPC: H01L23/538 ,  H01L25/065 ,  H01L21/768 ,  H01L21/48 ,  H01L21/50

    CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L25/0657

    Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.

    Recessed semiconductor devices, and associated systems and methods
    16.
    发明授权
    Recessed semiconductor devices, and associated systems and methods 有权

    公开(公告)号：US11646269B2

    公开(公告)日：2023-05-09

    申请号：US17243411

    申请日：2021-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrew M. Bayless ,  Brandon P. Wirz

    IPC: H01L23/538 ,  H01L25/065 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/53228 ,  H01L25/0657

    Abstract: Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.

    RECESSED SEMICONDUCTOR DEVICES, AND ASSOCIATED SYSTEMS AND METHODS
    17.
    发明申请
    RECESSED SEMICONDUCTOR DEVICES, AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20220352077A1

    公开(公告)日：2022-11-03

    申请号：US17243411

    申请日：2021-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrew M. Bayless ,  Brandon P. Wirz

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768

    Abstract: Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.

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