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    MEMORY DEVICE INTERFACE AND METHOD
    13.
    发明申请
    MEMORY DEVICE INTERFACE AND METHOD 审中-公开

    公开(公告)号：US20200272560A1

    公开(公告)日：2020-08-27

    申请号：US16797618

    申请日：2020-02-21

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

    IPC: G06F12/02 ,  H01L25/065

    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

    Device module having a plurality of dies electrically connected by posts
    14.
    发明授权
    Device module having a plurality of dies electrically connected by posts 有权

    公开(公告)号：US10325874B2

    公开(公告)日：2019-06-18

    申请号：US16175449

    申请日：2018-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Ashok Pachamuthu ,  Chan H. Yoo ,  Szu-Ying Ho ,  John F. Kaeding

    IPC: H01L23/34 ,  H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L21/768

    Abstract: Semiconductor device modules may include a redistribution layer and a first semiconductor die. A second semiconductor die may be located on the first semiconductor die. Posts may be located laterally adjacent to the first semiconductor die and the second semiconductor die. A first encapsulant may at least laterally surround the first semiconductor die, the second semiconductor die, and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on a second active surface of the second semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may be located over the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material. Conductive bumps may be connected to the redistribution layer on a side of the redistribution layer opposite the first semiconductor die.

    SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES
    15.
    发明申请
    SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES 审中-公开

    公开(公告)号：US20190067248A1

    公开(公告)日：2019-02-28

    申请号：US15686029

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Ashok Pachamuthu

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.

    HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND
    16.
    发明申请
    HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND 审中-公开

    公开(公告)号：US20190067034A1

    公开(公告)日：2019-02-28

    申请号：US15685940

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Ashok Pachamuthu ,  Chan H. Yoo ,  John F. Kaeding

    IPC: H01L21/48 ,  H01L23/48 ,  H01L23/50 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

    Abstract: Semiconductor devices with redistribution structures that do not include pre-formed substrates and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die attached to a redistribution structure and electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include one or more second semiconductor dies stacked on the first semiconductor die, wherein one or more of the first and second semiconductor dies are electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include a molded material over the first and/or second semiconductor dies and a surface of the redistribution structure.

    STACKED INTERPOSER STRUCTURES, AND RELATED METHODS
    17.
    发明申请
    STACKED INTERPOSER STRUCTURES, AND RELATED METHODS 有权

    公开(公告)号：US20250149530A1

    公开(公告)日：2025-05-08

    申请号：US19019138

    申请日：2025-01-13

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Chan H. Yoo

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/16

    Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

    LOW COST THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES
    18.
    发明申请
    LOW COST THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES 有权

    公开(公告)号：US20240371755A1

    公开(公告)日：2024-11-07

    申请号：US18774763

    申请日：2024-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Chan H. Yoo

    IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L25/065 ,  H01M50/414 ,  H05K9/00

    Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having a first metallization structure at the front side; (2) a semiconductor device package having a first side, a second side with a recess, and a second metallization structure at the first side and a contacting region exposed in the recess at the second side; (3) an interconnect structure at least partially positioned in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another.

    SEMICONDUCTOR DEVICES WITH FLEXIBLE REINFORCEMENT STRUCTURE
    19.
    发明公开
    SEMICONDUCTOR DEVICES WITH FLEXIBLE REINFORCEMENT STRUCTURE 审中-公开

    公开(公告)号：US20240304465A1

    公开(公告)日：2024-09-12

    申请号：US18668887

    申请日：2024-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Chan H. Yoo

    IPC: H01L21/56 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31

    CPC classification number: H01L21/56 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114

    Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface facing the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 μm. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.

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