公开(公告)号：US20210210126A1

公开(公告)日：2021-07-08

申请号：US16737139

申请日：2020-01-08

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: G11C7/22 ,  G11C7/06 ,  G11C16/26 ,  G11C11/4093 ,  G06F13/16

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

公开(公告)号：US20190027203A1

公开(公告)日：2019-01-24

申请号：US16140281

申请日：2018-09-24

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.

公开(公告)号：US20180005683A1

公开(公告)日：2018-01-04

申请号：US15689211

申请日：2017-08-29

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.

公开(公告)号：US08797819B2

公开(公告)日：2014-08-05

申请号：US13899192

申请日：2013-05-21

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Mikhail Nagoga ,  Serguei Okhonin

IPC: G11C7/00

CPC classification number: G11C11/4096 ,  G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.

Abstract translation: 描述了包括其的电路的半导体器件及其操作方法。 该器件包括一个包括一个晶体管的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 存储在设备的存储单元中的数据可以在单个时钟周期内刷新。

公开(公告)号：US20240257855A1

公开(公告)日：2024-08-01

申请号：US18403498

申请日：2024-01-03

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Eric Carman

IPC: G11C11/22 ,  G11C5/06 ,  G11C5/10

CPC classification number: G11C11/221 ,  G11C5/063 ,  G11C5/10 ,  G11C11/2273

Abstract: Techniques and configurations for electronic memory are described. An apparatus may include a first set of memory cells coupled with a first plate line and a word line, where a memory cell in the first set of memory cells may be coupled with a first bit line, and a second set of memory cells coupled with a second plate line and the word line, where a memory cell of the second set of memory cells may be coupled with a second bit line. The apparatus may also include a sense component having a first node coupled with the first bit line and a first capacitor and a second node coupled with the second bit line and a second capacitor. Also, a set of capacitors may be coupled with both nodes. The capacitors may support adjustment of the voltage of the nodes of the sense component.

公开(公告)号：US20230352080A1

公开(公告)日：2023-11-02

申请号：US18217205

申请日：2023-06-30

Applicant: Micron Technology, Inc

Inventor： Eric Carman ,  Daniele Vimercati

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C7/065 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4096

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

公开(公告)号：US20150302898A1

公开(公告)日：2015-10-22

申请号：US14789453

申请日：2015-07-01

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  H01L27/102

CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.

Abstract translation: 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，技术可以被实现为直接注入半导体存储器件，其包括耦合到源极线的第一区域，耦合到位线的第二区域。 直接注入半导体存储器件还可以包括与字线间隔开并且电容耦合到字线的主体区域，其中主体区域电浮动并且设置在第一区域和第二区域之间。 直接注入半导体存储器件还可以包括耦合到载体注入管线的第三区域，其被配置为通过第二区域将电荷注入体区域。

公开(公告)号：US20250078903A1

公开(公告)日：2025-03-06

申请号：US18790372

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Eric Carman ,  Kamal M. Karda

IPC: G11C11/4074 ,  G11C11/4091 ,  H10B12/00

Abstract: Systems, methods, and apparatus are provided for discharging an access device in a memory device. An example structure includes a memory device having a local sense line and a bleeder device coupled to the local sense line and a bleeder supply. The memory device can also include a sense line multiplexor coupled to the local sense line and a global sense line, and a sense amplifier coupled to the global sense line. The sense amplifier can be configured to sense and latch a voltage of the global sense line in response to the memory device receiving a command. The memory device can further include a plurality of access devices coupled to the local sense line, a plurality of capacitors coupled to the plurality of access devices, and a plate voltage supply, separate from the bleeder supply, coupled to the plurality of capacitors.

公开(公告)号：US12131771B2

公开(公告)日：2024-10-29

申请号：US17860470

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: G11C11/4091

CPC classification number: G11C11/4091

Abstract: Sense amplifiers for memory devices include latch transistors that are used to latch values based on charges in memory cells. A first latch transistor applies a reference voltage to a first gut node of the sense amplifier via one of these latch transistors. The sense amplifier also applies a charge to a second gut node from a memory cell corresponding to the sense amplifier. The sense amplifier also latches a value in the sense amplifier based on a relationship between the reference voltage and the charge.

公开(公告)号：US11127443B2

公开(公告)日：2021-09-21

申请号：US16737139

申请日：2020-01-08

Applicant: Micron Technology, inc.

Inventor： Eric Carman

IPC: G11C7/22 ,  G11C7/06 ,  G06F13/16 ,  G11C11/4093 ,  G11C16/26

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.