公开(公告)号：US08861247B2

公开(公告)日：2014-10-14

申请号：US13964927

申请日：2013-08-12

Applicant: Micron Technology, Inc.

Inventor： Yogesh Luthra ,  Serguei Okhonin ,  Mikhail Nagoga

IPC: G11C5/10

CPC classification number: H01L27/0664 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/4094 ,  G11C2211/4016 ,  H01L29/7302 ,  H01L29/732

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.

Abstract translation: 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，可以将技术实现为用于偏置直接注入半导体存储器件的方法。 该方法可以包括经由位线将第一电压电势施加到第一N掺杂区域，并且经由源极线将第二电压电势施加到第二N掺杂区域。 该方法还可以包括将第三电压电位施加到字线，其中字线与电浮置并且设置在第一N掺杂区域和第二N掺杂区域之间的体区间隔开并且电容耦合 。 该方法还可以包括经由载体注入管线向P型衬底施加第四电压电位。

公开(公告)号：US09425190B2

公开(公告)日：2016-08-23

申请号：US14503784

申请日：2014-10-01

Applicant: Micron Technology, Inc.

Inventor： Yogesh Luthra ,  Serguei Okhonin ,  Mikhail Nagoga

IPC: G11C16/10 ,  H01L27/06 ,  G11C5/02 ,  G11C5/06 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/4094 ,  G11C7/00 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L27/0664 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/4094 ,  G11C2211/4016 ,  H01L29/7302 ,  H01L29/732

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.

公开(公告)号：US08797819B2

公开(公告)日：2014-08-05

申请号：US13899192

申请日：2013-05-21

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Mikhail Nagoga ,  Serguei Okhonin

IPC: G11C7/00

CPC classification number: G11C11/4096 ,  G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.

Abstract translation: 描述了包括其的电路的半导体器件及其操作方法。 该器件包括一个包括一个晶体管的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 存储在设备的存储单元中的数据可以在单个时钟周期内刷新。

公开(公告)号：US09331083B2

公开(公告)日：2016-05-03

申请号：US14458569

申请日：2014-08-13

Applicant: Micron Technology, Inc.

Inventor： Serguei Okhonin ,  Viktor Koldiaev ,  Mikhail Nagoga ,  Yogesh Luthra

IPC: H01L21/8234 ,  H01L27/108 ,  G11C11/39 ,  G11C11/403 ,  G11C11/404 ,  H01L27/102 ,  H01L29/78 ,  G11C16/10 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L27/10844 ,  G11C11/39 ,  G11C11/403 ,  G11C11/404 ,  G11C16/10 ,  G11C2211/4016 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823475 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.

公开(公告)号：US08817534B2

公开(公告)日：2014-08-26

申请号：US13899177

申请日：2013-05-21

Applicant: Micron Technology, Inc.

Inventor： Serguei Okhonin ,  Viktor I Koldiaev ,  Mikhail Nagoga ,  Yogesh Luthra

IPC: G11C16/04 ,  G11C11/24 ,  H01L29/788

CPC classification number: H01L27/10844 ,  G11C11/39 ,  G11C11/403 ,  G11C11/404 ,  G11C16/10 ,  G11C2211/4016 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823475 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.

Abstract translation: 公开了一种用于提供半导体存储器件的技术。 在一个特定的示例性实施例中，可以将技术实现为包括第一区域和第二区域的装置。 该装置还可以包括设置在第一区域和第二区域之间并且电容耦合到多个字线的主体区域，其中多个字线中的每一个电容耦合到身体区域的不同部分。