公开(公告)号：US20250159878A1

公开(公告)日：2025-05-15

申请号：US19022599

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H10B41/30 ,  H01L21/768 ,  H10B41/20 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20250159877A1

公开(公告)日：2025-05-15

申请号：US19022523

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H10B41/30 ,  H01L21/768 ,  H10B41/20 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20200052134A1

公开(公告)日：2020-02-13

申请号：US16659478

申请日：2019-10-21

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Kunal Shrotri ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Duo Mao ,  Zhixin Xu ,  Ee Ee Eng ,  Jie Li ,  Dong Liang

IPC: H01L29/792 ,  G11C16/04 ,  G11C16/08 ,  H01L27/1157 ,  H01L29/66 ,  H01L21/28

Abstract: A method of forming Si3Nx, where “x” is less than 4 and at least 3, comprises decomposing a Si-comprising precursor molecule into at least two decomposition species that are different from one another, at least one of the at least two different decomposition species comprising Si. An outer substrate surface is contacted with the at least two decomposition species. At least one of the decomposition species that comprises Si attaches to the outer substrate surface to comprise an attached species. The attached species is contacted with a N-comprising precursor that reacts with the attached species to form a reaction product comprising Si3Nx, where “x” is less than 4 and at least 3. Other embodiments are disclosed, including constructions made in accordance with method embodiments of the invention and constructions independent of method of manufacture.

公开(公告)号：US20190043890A1

公开(公告)日：2019-02-07

申请号：US16158039

申请日：2018-10-11

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/532 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US10157933B2

公开(公告)日：2018-12-18

申请号：US15133119

申请日：2016-04-19

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L29/792 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US10121799B2

公开(公告)日：2018-11-06

申请号：US15851532

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Tom J. John ,  Kunal Shrotri ,  Anish A. Khandekar ,  Aaron R. Wilson ,  John D. Hopkins ,  Derek F. Lundberg

IPC: H01L27/11582 ,  H01L21/033 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11556

Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US09075317B2

公开(公告)日：2015-07-07

申请号：US14480754

申请日：2014-09-09

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Ezequiel Vidal Russell ,  Chung-Yi Lee

IPC: G03F1/00 ,  G03F1/32 ,  G03F1/26 ,  G03F1/30 ,  G03F1/38 ,  G03F1/68

CPC classification number: G03F1/32 ,  G03F1/00 ,  G03F1/26 ,  G03F1/30 ,  G03F1/36 ,  G03F1/38 ,  G03F1/68

Abstract: A photomask includes a substrate having a device region and an adjacent edge region over transparent material. The device region includes spaced primary features of constant pitch at least adjacent the edge region. The edge region includes spaced sub-resolution assist features of the constant pitch of the spaced primary features at least adjacent the device region and which are off-phase by from about 30° to about 150° from +/−180°. Additional embodiments, including methods, are disclosed.

Abstract translation: 光掩模包括具有在透明材料上的器件区域和相邻边缘区域的衬底。 器件区域包括至少邻近边缘区域的恒定间距的间隔的主要特征。 边缘区域包括间隔开的主要特征的至少相邻于器件区域的恒定间距的间隔的次分辨率辅助特征，并且与+/- 180°相差约30°至约150°。 公开了包括方法的其它实施例。

公开(公告)号：US11937429B2

公开(公告)日：2024-03-19

申请号：US17556704

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/1157 ,  H01L23/528 ,  H01L23/532 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/528 ,  H01L23/53257 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US11282845B2

公开(公告)日：2022-03-22

申请号：US15685690

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11551 ,  H01L27/11541 ,  H01L21/768 ,  H01L27/11548 ,  H01L27/11575

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US11239252B2

公开(公告)日：2022-02-01

申请号：US16907967

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.