公开(公告)号：US20180151415A1

公开(公告)日：2018-05-31

申请号：US15881539

申请日：2018-01-26

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US09899254B2

公开(公告)日：2018-02-20

申请号：US15471420

申请日：2017-03-28

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US20160204022A1

公开(公告)日：2016-07-14

申请号：US15080060

申请日：2016-03-24

Applicant: Micron Technology, Inc.

Inventor： Giulio Albini

IPC: H01L21/768 ,  H01L45/00 ,  H01L27/24 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/7684 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.

Abstract translation: 诸如相变存储器件的半导体器件和结构包括耦合到外围区域中的外围导电触点的外围导电焊盘。 阵列区域可以包括耦合到导线的存储单元。 形成这样的半导体器件和结构的方法包括从周边区域去除存储单元材料，然后从阵列区域选择性地去除存储单元材料的部分，以限定阵列区域中的各个存储单元。 附加的方法包括使用外围导电焊盘和/或间隔物材料在外围导电焊盘上平坦化结构作为平坦化停止材料。 另外的方法包括部分地限定阵列区域中的存储单元，之后形成外围导电触点，然后完全限定存储单元。

公开(公告)号：US09189444B2

公开(公告)日：2015-11-17

申请号：US14455718

申请日：2014-08-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giulio Albini ,  Emanuele Confalonieri

IPC: G06F12/00 ,  G06F13/42 ,  G06F3/06 ,  G06F13/40 ,  G06F12/14

CPC classification number: G06F12/1466 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/14 ,  G06F13/1668 ,  G06F13/4036 ,  G06F13/4221 ,  G06F2212/1052

Abstract: Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.

Abstract translation: 本文公开的主题涉及包括存储器和控制器的控制器，诸如控制器，其与共享至少一个存储器块的两个或多个接口之间的操作转换相关联地确定块锁定状态。 该装置可以支持单通道或多通道存储器访问，写保护状态逻辑或各种接口优先级方案。

公开(公告)号：US08634242B2

公开(公告)日：2014-01-21

申请号：US13720045

申请日：2012-12-19

Applicant: Micron Technology, Inc.

Inventor： Alessandro Grossi ,  Giulio Albini ,  Anna Maria Conti

IPC: G11C16/00

CPC classification number: H01L21/768 ,  H01L23/48 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.

Abstract translation: 本文公开的主题涉及多级闪存和形成其的处理流程。

公开(公告)号：US20130147045A1

公开(公告)日：2013-06-13

申请号：US13720045

申请日：2012-12-19

Applicant: Micron Technology, Inc.

Inventor： Alessandro Grossi ,  Giulio Albini ,  Anna Maria Conti

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/768 ,  H01L23/48 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.

Abstract translation: 本文公开的主题涉及多级闪存和形成其的处理流程。

公开(公告)号：US20220367799A1

公开(公告)日：2022-11-17

申请号：US17875691

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Giulio Albini

IPC: H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for low resistance via contacts in a memory device are described. A via may be formed so as to protrude from a surrounding material. A barrier material may be formed above an array area and also above the via. After a first layer of an access line material is formed above the barrier material, a planarization process may be applied until the top of the via is exposed. The planarization process may remove the access line material and the barrier material from above the via, but the access line material and the barrier material may remain above the array area. The first layer of the access line material may protect the unremoved barrier material during the planarization process. A second layer of the access line material may be formed above the first layer of the access line material and in direct contact with the via.

公开(公告)号：US20210305506A1

公开(公告)日：2021-09-30

申请号：US16832324

申请日：2020-03-27

Applicant: Micron Technology, Inc.

Inventor： Giulio Albini

IPC: H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for low resistance via contacts in a memory device are described. A via may be formed so as to protrude from a surrounding material. A barrier material may be formed above an array area and also above the via. After a first layer of an access line material is formed above the barrier material, a planarization process may be applied until the top of the via is exposed. The planarization process may remove the access line material and the barrier material from above the via, but the access line material and the barrier material may remain above the array area. The first layer of the access line material may protect the unremoved barrier material during the planarization process. A second layer of the access line material may be formed above the first layer of the access line material and in direct contact with the via.

公开(公告)号：US09728449B2

公开(公告)日：2017-08-08

申请号：US15080060

申请日：2016-03-24

Applicant: Micron Technology, Inc.

Inventor： Giulio Albini

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/7684 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.

公开(公告)号：US09343669B2

公开(公告)日：2016-05-17

申请号：US14739452

申请日：2015-06-15

Applicant: Micron Technology, Inc.

Inventor： Giulio Albini

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L21/7684 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.

Abstract translation: 诸如相变存储器件的半导体器件和结构包括耦合到外围区域中的外围导电触点的外围导电焊盘。 阵列区域可以包括耦合到导线的存储单元。 形成这样的半导体器件和结构的方法包括从周边区域去除存储单元材料，然后从阵列区域选择性地去除存储单元材料的部分，以限定阵列区域中的各个存储单元。 附加的方法包括使用外围导电焊盘和/或间隔物材料在外围导电焊盘上平坦化结构作为平坦化停止材料。 另外的方法包括部分地限定阵列区域中的存储单元，之后形成外围导电触点，然后完全限定存储单元。