公开(公告)号：US20240312499A1

公开(公告)日：2024-09-19

申请号：US18672339

申请日：2024-05-23

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Yang Lu

IPC: G11C7/10 ,  H03K19/017 ,  H03K19/173

CPC classification number: G11C7/109 ,  G11C7/1087 ,  H03K19/01742 ,  H03K19/1737

Abstract: The subject application is directed to die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

公开(公告)号：US12020771B2

公开(公告)日：2024-06-25

申请号：US17818413

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Yang Lu

IPC: G11C7/10 ,  H03K19/017 ,  H03K19/173

CPC classification number: G11C7/109 ,  G11C7/1087 ,  H03K19/01742 ,  H03K19/1737

Abstract: Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

公开(公告)号：US20240161794A1

公开(公告)日：2024-05-16

申请号：US18407062

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyunyoo Lee

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093

Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

公开(公告)号：US11747992B2

公开(公告)日：2023-09-05

申请号：US17349634

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Taeksang Song ,  Kang-Yong Kim

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7211

Abstract: Methods, systems, and devices for memory wear management are described. A device may include an interface controller and a non-volatile memory. The interface controller may manage wear-leveling procedures for memory banks in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear-leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then transfer the data to the non-volatile memory so that the non-volatile memory can write the data to a second row of the memory bank.

公开(公告)号：US11587633B2

公开(公告)日：2023-02-21

申请号：US17349612

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Hyunyoo Lee ,  Saira Samar Malik ,  Kang-Yong Kim

IPC: G11C29/10 ,  G11C29/36 ,  G11C29/14 ,  G11C29/18 ,  G11C29/12

Abstract: Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

公开(公告)号：US20220398042A1

公开(公告)日：2022-12-15

申请号：US17586534

申请日：2022-01-27

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G06F3/06

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

公开(公告)号：US20250095699A1

公开(公告)日：2025-03-20

申请号：US18962783

申请日：2024-11-27

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Taeksang Song

IPC: G11C7/10 ,  G11C8/06 ,  G11C11/4074

Abstract: Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

公开(公告)号：US20240371460A1

公开(公告)日：2024-11-07

申请号：US18651357

申请日：2024-04-30

Applicant: Micron Technology, Inc.

Inventor： Smruti Subhash Jhaveri ,  Hyunyoo Lee

IPC: G11C29/56

Abstract: During a command bus training (CBT), interconnected memory dice are accessed in a sequence determined (e.g., predetermined) by a bit sequence generator and via a shared data link for retrieving a respective set of feedback data of the CBT from each memory dice. This eliminates a need to individually train and/or control interconnected memory dice for the CBT; thereby, providing a flexible and scalable architecture that can accommodate a range of memory densities (e.g., a number of memory dice that are interconnected) and making it a valuable solution for high-performance memory applications.

公开(公告)号：US11947841B2

公开(公告)日：2024-04-02

申请号：US17586534

申请日：2022-01-27

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0602 ,  G06F3/0673

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

公开(公告)号：US11804261B2

公开(公告)日：2023-10-31

申请号：US17662325

申请日：2022-05-06

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang Yong Kim

IPC: G11C11/4093 ,  G06F13/40 ,  G11C11/4076 ,  H03F3/45 ,  H03K19/00

CPC classification number: G11C11/4093 ,  G06F13/4022 ,  G11C11/4076 ,  H03F3/45 ,  H03K19/0005 ,  H03F2203/45151

Abstract: This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.