公开(公告)号：US11791260B2

公开(公告)日：2023-10-17

申请号：US17165276

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B12/00

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B12/30

Abstract: Devices, systems, and methods for forming twisted conductive lines are described herein. One method includes: forming a first row and a second row of a first number of vertical conductive line contacts, the vertical contacts in each row are arrayed in a first horizontal direction and the first row is spaced from the second row in a second horizontal direction; forming a number of conductive lines with curved portions, each conductive line making contact with alternating conductive line contacts of the first and second rows of the first number of vertical conductive line contacts; and forming a second number of conductive lines with one or more curved portions, each conductive line making contact with the remaining ones of the conductive line contacts of the first and second rows of the first number of vertical conductive line contacts that have not been contacted by the first number of conductive lines.

公开(公告)号：US11696432B2

公开(公告)日：2023-07-04

申请号：US17060356

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim ,  Kyuseok Lee ,  Sangmin Hwang ,  Mark Zaleski

IPC: H01L27/108 ,  H10B12/00 ,  G11C5/02 ,  G11C5/10 ,  H01L27/06

CPC classification number: H10B12/30 ,  G11C5/025 ,  G11C5/10 ,  H01L27/0688

Abstract: Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

公开(公告)号：US20230135653A1

公开(公告)日：2023-05-04

申请号：US17513489

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee ,  Sangmin Hwang ,  Byung Yoon Kim

IPC: H01L27/105 ,  H01L27/092 ,  H01L23/528 ,  H01L23/535 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8238

Abstract: An apparatus includes a substrate and a memory cell array disposed on the substrate. The apparatus also includes a logic cell disposed on the substrate in a peripheral region adjacent the memory cell array. The apparatus further includes a trench isolation region disposed in the substrate in the peripheral region. The trench isolation region either separates a first active area of the logic cell from a second active area of the logic cell or separates the logic cell from an adjacent logic cell. The logic cell includes a connection line that is buried within the trench isolation region. The connection line can be formed as an extension of a buried word line in the memory cell array region during a same fabrication process that forms the corresponding buried word line. By extending the buried word line into the peripheral region, the buried connection line can be formed without additional processing.

公开(公告)号：US20220068351A1

公开(公告)日：2022-03-03

申请号：US17006730

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Takefumi Shirako ,  Masahiro Yokomichi ,  Kyuseok Lee ,  Sangmin Hwang

IPC: G11C11/408

Abstract: In some examples, a subword driver block of a memory device includes a plurality of active regions of a first type and a plurality of active regions of a second type adjacent to the plurality of active regions of the first type. The subword driver block further includes a plurality of first gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of first transistors, and a plurality of second gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of second transistors. Each of the second transistors is shared by a first subword driver and a second subword driver. Each of the second transistors may include a drain and a source respectively coupled to a first and second word line, which are driven by the first subword driver and the second subword driver, respectively.

公开(公告)号：US20210020210A1

公开(公告)日：2021-01-21

申请号：US17064545

申请日：2020-10-06

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee

IPC: G11C7/12 ,  G11C8/08 ,  G11C7/06

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier that is configured to simultaneously precharge sensing nodes therein and compensate for threshold voltage mismatches between any transistors therein. The sense amplifier may be configured to charge gut nodes therein without connecting to a separate precharging voltage.

公开(公告)号：US20240373624A1

公开(公告)日：2024-11-07

申请号：US18774420

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H10B12/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

公开(公告)号：US20240312504A1

公开(公告)日：2024-09-19

申请号：US18441962

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Guy S. Perry, IV ,  Shinichi Miyatake ,  Kyuseok Lee

IPC: G11C8/08 ,  G11C8/14

CPC classification number: G11C8/08 ,  G11C8/14

Abstract: Active materials for reducing hot electron-induced punch-through and related apparatuses and computing systems are disclosed. An apparatus includes a first active material, a second active material, a third active material, and a fourth active material. The first active material includes a first outside edge and a first inside edge. The first outside edge defines a first notch. The second active material is spaced at substantially a minimum tolerance distance from the first active material. The third active material is spaced at substantially the minimum tolerance distance from the second active material. The fourth active material includes a second outside edge and a second inside edge. The second inside edge is spaced at substantially the minimum tolerance distance from the third active material. The second outside edge defines a second notch. A computing system includes a memory device including a subwordline driver including the apparatus.

公开(公告)号：US12063797B2

公开(公告)日：2024-08-13

申请号：US17513489

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee ,  Sangmin Hwang ,  Byung Yoon Kim

IPC: H10B99/00 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H10B99/00 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092

Abstract: An apparatus includes a substrate and a memory cell array disposed on the substrate. The apparatus also includes a logic cell disposed on the substrate in a peripheral region adjacent the memory cell array. The apparatus further includes a trench isolation region disposed in the substrate in the peripheral region. The trench isolation region either separates a first active area of the logic cell from a second active area of the logic cell or separates the logic cell from an adjacent logic cell. The logic cell includes a connection line that is buried within the trench isolation region. The connection line can be formed as an extension of a buried word line in the memory cell array region during a same fabrication process that forms the corresponding buried word line. By extending the buried word line into the peripheral region, the buried connection line can be formed without additional processing.

公开(公告)号：US12052858B2

公开(公告)日：2024-07-30

申请号：US18131097

申请日：2023-04-05

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H10B12/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B12/50 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/09 ,  H10B12/30

Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

公开(公告)号：US20220246525A1

公开(公告)日：2022-08-04

申请号：US17165276

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H01L23/528 ,  H01L27/108 ,  H01L23/522 ,  H01L21/768

Abstract: Devices, systems, and methods for forming twisted conductive lines are described herein. One method includes: forming a first row and a second row of a first number of vertical conductive line contacts, the vertical contacts in each row are arrayed in a first horizontal direction and the first row is spaced from the second row in a second horizontal direction; forming a number of conductive lines with curved portions, each conductive line making contact with alternating conductive line contacts of the first and second rows of the first number of vertical conductive line contacts; and forming a second number of conductive lines with one or more curved portions, each conductive line making contact with the remaining ones of the conductive line contacts of the first and second rows of the first number of vertical conductive line contacts that have not been contacted by the first number of conductive lines.