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公开(公告)号:US09773844B2
公开(公告)日:2017-09-26
申请号:US14970602
申请日:2015-12-16
Applicant: Micron Technology, Inc.
Inventor: Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini , Gabriel L. Donadio
CPC classification number: H01L27/2481 , G11C5/063 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.
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公开(公告)号:US20170207273A1
公开(公告)日:2017-07-20
申请号:US15479403
申请日:2017-04-05
Applicant: Micron Technology, Inc.
Inventor: Samuele Sciarrillo , Marcello Ravasio
CPC classification number: H01L27/2427 , H01L27/224 , H01L27/226 , H01L27/228 , H01L27/2409 , H01L27/2436 , H01L27/2445 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/148 , H01L45/1675
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
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公开(公告)号:US20150243885A1
公开(公告)日:2015-08-27
申请号:US14189265
申请日:2014-02-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Samuele Sciarrillo
IPC: H01L45/00
CPC classification number: H01L27/2481 , H01L27/2427 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.
Abstract translation: 所公开的技术通常涉及集成电路器件,特别涉及交叉点存储器阵列及其制造方法。 在一个方面,存储器阵列的存储器件包括衬底和形成在电连接到第一和第二导电线之间的存储单元组。 存储单元堆叠包括衬底上的第一存储器元件和形成在第一元件上的第二存储器元件,其中第一和第二存储元件中的一个包括存储元件,第一和第二存储元件中的另一个包括选择器元件 。 存储单元堆叠还包括彼此相对的第一对侧壁和彼此相对并与第一对侧壁相交的第二对侧壁。 存储器件还包括形成在第一对侧壁的下部上的第一保护介电绝缘材料和形成在第一保护介电绝缘材料上并进一步形成在第一对侧壁的上部上的隔离电介质。
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公开(公告)号:US20150243708A1
公开(公告)日:2015-08-27
申请号:US14189490
申请日:2014-02-25
Applicant: MICRON TECHNOLOGY, INC
Inventor: Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
CPC classification number: H01L27/2463 , H01L27/2427 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
Abstract translation: 所公开的技术通常涉及集成电路器件,特别涉及交叉点存储器阵列及其制造方法。 在一个方面,一种制造交叉点存储器阵列的方法包括形成存储单元材料堆,所述存储单元材料堆在第一活性材料上包括第一活性材料和第二活性材料,其中第一和第二活性材料之一包括存储材料 并且第一和第二活性材料中的另一个包括选择材料。 制造交叉点阵列的方法还包括对存储单元材料堆叠进行图案化,其包括通过存储单元材料堆叠的第一和第二活性材料中的至少一个的蚀刻,在至少一个的至少一个的侧壁上形成保护衬垫 在蚀刻通过第一和第二活性材料之一之后蚀刻第一和第二活性材料,并且在第一和第二活性材料之一的侧壁上形成保护衬垫之后进一步蚀刻存储单元材料堆叠。
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公开(公告)号:US10854674B2
公开(公告)日:2020-12-01
申请号:US15693102
申请日:2017-08-31
Applicant: Micron Technology, Inc.
Inventor: Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号:US10777743B2
公开(公告)日:2020-09-15
申请号:US15792842
申请日:2017-10-25
Applicant: Micron Technology, Inc.
Inventor: Marcello Ravasio , Samuele Sciarrillo , Andrea Gotti
IPC: H01L45/00 , H01L27/105 , H01L21/28 , H01L27/24 , H01L27/22 , H01L21/3213
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
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公开(公告)号:US20190355789A1
公开(公告)日:2019-11-21
申请号:US16420483
申请日:2019-05-23
Applicant: Micron Technology, Inc.
Inventor: Ombretta Donghi , Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini
Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
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公开(公告)号:US20170365642A1
公开(公告)日:2017-12-21
申请号:US15693102
申请日:2017-08-31
Applicant: Micron Technology, Inc.
Inventor: Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
CPC classification number: H01L27/2463 , H01L27/2427 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号:US20160020256A1
公开(公告)日:2016-01-21
申请号:US14867185
申请日:2015-09-28
Applicant: Micron Technology, Inc.
Inventor: Samuele Sciarrillo , Marcello Ravasio
CPC classification number: H01L27/2427 , H01L27/224 , H01L27/226 , H01L27/228 , H01L27/2409 , H01L27/2436 , H01L27/2445 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/148 , H01L45/1675
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
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20.
公开(公告)号:US20150137061A1
公开(公告)日:2015-05-21
申请号:US14086460
申请日:2013-11-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Ombretta Donghi , Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini
CPC classification number: H01L27/2463 , H01L27/2427 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
Abstract translation: 公开了一种制造存储器件的方法。 一方面,该方法包括对沿第一方向延伸的第一导电线图案化。 该方法还包括在对第一导线图案化之后,在第一导电线上形成存储单元堆叠的独立柱。 形成独立的支柱包括在导电线上沉积包括选择材料和储存材料的存储单元堆叠,并且使存储单元堆叠构图以形成独立柱。 该方法还包括在图案化存储单元堆叠之后在柱上图形化第二导线,第二导线沿与第一方向交叉的第二方向延伸。
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