公开(公告)号：US20140254265A1

公开(公告)日：2014-09-11

申请号：US14282810

申请日：2014-05-20

Applicant: Micron Technology, Inc.

Inventor： Seiichi Aritome ,  Di Li

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate types, and capacitively coupled with control gates of the first gate types. The second gate types may be multilevel cell (MLC) devices, and pass voltage applied to the control gates of the first gate types may be utilized to reduce programming voltages utilized to reach memory states of the MLC devices. Some embodiments include NAND cell units, and some embodiments include methods of forming NAND cell units. Also, some embodiments include methods of programming NAND cell unit string gates in which programming voltage applied to a first string gate is held below a threshold, and pass voltage applied to an adjacent string gate is increased and utilized to program the first string gate.

Abstract translation: 一些实施例包括沿NAND串的交替的第一和第二栅极类型的利用，其中第二栅极类型具有比第一栅极类型的浮置栅极厚的浮动栅极，并且与第一栅极类型的栅极电容耦合。 第二栅极类型可以是多电平单元（MLC）器件，并且施加到第一栅极类型的控制栅极的通过电压可以用于减少用于达到MLC器件的存储器状态的编程电压。 一些实施例包括NAND单元单元，并且一些实施例包括形成NAND单元单元的方法。 此外，一些实施例包括编程NAND单元单元串门的方法，其中施加到第一串门的编程电压被保持在阈值以下，并且增加施加到相邻串门的通过电压并用于对第一串门进行编程。

公开(公告)号：US20140160843A1

公开(公告)日：2014-06-12

申请号：US14099530

申请日：2013-12-06

Applicant: Micron Technology, Inc.

Inventor： Seiichi Aritome

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states.

Abstract translation: 本公开包括用于操作非易失性多电平存储器单元的方法，设备，模块和系统。 一种方法实施例包括向耦合到行选择线的第一单元分配可以对第一单元编程的第一数量的编程状态。 该方法包括将耦合到行选择线的第二单元分配给可编程第二单元的第二数量的编程状态，其中第二数量的编程状态大于第一数量的编程状态。 该方法包括在将第二单元编程到第二数量的编程状态之前将第一单元编程为第一数量的编程状态之一。

公开(公告)号：US20130237031A1

公开(公告)日：2013-09-12

申请号：US13866698

申请日：2013-04-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seiichi Aritome

IPC: H01L21/762

CPC classification number: H01L21/762 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.

Abstract translation: 一种存储器阵列，包括相对于彼此具有隔离的栅极间电介质区域的晶体管。 晶体管被形成为使得阵列中的每个晶体管具有电荷存储区域，例如浮置栅极，控制栅极和栅极之间的介电层。 每个晶体管的栅极间电介质层与阵列中的每个其它晶体管的栅极间电介质隔离。

公开(公告)号：US20170053701A1

公开(公告)日：2017-02-23

申请号：US15341410

申请日：2016-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seiichi Aritome

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/102 ,  G11C16/26

Abstract: A trim set register for a memory device has a plurality of individual trim settings. Each trim setting has a program trim value, a step-up trim value, and a program pulse width. A trim setting may be assigned to a portion of the memory device based on a program speed of the portion of the memory device.

Abstract translation: 用于存储器件的修整设置寄存器具有多个单独的修整设置。 每个修剪设置都有一个程序修剪值，一个升压修剪值和一个编程脉冲宽度。 可以基于存储器件的该部分的程序速度将修剪设置分配给存储器件的一部分。

公开(公告)号：US20150221378A1

公开(公告)日：2015-08-06

申请号：US14688149

申请日：2015-04-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seiichi Aritome

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/102 ,  G11C16/26

Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

公开(公告)号：US08580645B2

公开(公告)日：2013-11-12

申请号：US13786889

申请日：2013-03-06

Applicant: Micron Technology, Inc.

Inventor： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。