公开(公告)号：US20240021521A1

公开(公告)日：2024-01-18

申请号：US17812616

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Martin Jared Barclay ,  Harsh Narendrakumar Jain ,  Yiping Wang

IPC: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

Abstract: Methods, systems, and devices for staircase structures for accessing three-dimensional (3D) memory arrays are described. A memory system may include an access region (e.g., a staircase region) that includes circuitry for accessing memory cells at respective levels of memory cells. The access region may include a channel through which a conductive pillar may couple a word line at a level of memory cells with decoder circuitry. During manufacture of the memory system, a channel material may be formed in the channel and etched to form a corner portion in the channel. During a partitioning of the channel, a nitride material over the corner portion may be etched and some of the corner portion may remain in the channel, which may prevent formation of a trench that may cause the conductive pillar to be uncoupled from the word line.

公开(公告)号：US11721629B2

公开(公告)日：2023-08-08

申请号：US17381991

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Yiping Wang ,  Jordan D. Greenlee ,  John Hopkins

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

公开(公告)号：US11621273B2

公开(公告)日：2023-04-04

申请号：US15931421

申请日：2020-05-13

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Andrew Li ,  Haoyu Li ,  Matthew J. King ,  Wei Yeeng Ng ,  Yongjun Jeff Hu

IPC: H01L27/00 ,  H01L27/11582 ,  H01L27/11524 ,  H01L21/283 ,  H01L27/1157 ,  H01L21/306 ,  H01L27/11556

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230022792A1

公开(公告)日：2023-01-26

申请号：US17381991

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Yiping Wang ,  Jordan D. Greenlee ,  John Hopkins

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

公开(公告)号：US11164873B2

公开(公告)日：2021-11-02

申请号：US16420429

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Silvia Borsari ,  Stian E. Wood ,  Haoyu Li ,  Yiping Wang

IPC: H01L27/108 ,  H01L21/768 ,  H01L27/08

Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.

公开(公告)号：US12256546B2

公开(公告)日：2025-03-18

申请号：US18386346

申请日：2023-11-02

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Andrew Li ,  Haoyu Li ,  Matthew J. King ,  Wei Yeeng Ng ,  Yongjun Jeff Hu

IPC: H10B43/00 ,  H01L21/283 ,  H01L21/306 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240373636A1

公开(公告)日：2024-11-07

申请号：US18621738

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David H. Wells ,  Yiping Wang ,  Mojtaba Asadirad ,  Harsh Narendrakumar Jain

IPC: H10B43/27 ,  H10B41/27

Abstract: A method of forming a microelectronic device comprises forming a preliminary stack structure over a source structure. The preliminary stack structure comprises a vertically alternating sequence of insulative material and sacrificial material arranged in preliminary tiers. The method comprises forming a staircase structure having steps comprising edges of at least some of the preliminary tiers of the preliminary stack structure, forming implant regions within exposed portions of the sacrificial material at the steps of the staircase structure, forming openings extending through the preliminary stack structure to the source structure and within a horizontal area of the staircase structure, replacing portions of the sacrificial material with conductive structures, forming strapping structures comprising conductive material, at locations vacated by the implant regions, laterally adjacent to the conductive structures at the steps of the staircase structure, and forming conductive contacts within the openings. Additional methods and microelectronic devices are also described.

公开(公告)号：US11972978B2

公开(公告)日：2024-04-30

申请号：US17736365

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Jordan D. Greenlee ,  Collin Howder

IPC: H10B41/10 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B41/30 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L21/76879 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalls of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240113012A1

公开(公告)日：2024-04-04

申请号：US17937360

申请日：2022-09-30

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Yiping Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L23/53295 ,  H01L27/11556 ,  H01L27/11582

Abstract: A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure vertically span substantially the same tiers of the stack structure as the liner structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20240105510A1

公开(公告)日：2024-03-28

申请号：US17950640

申请日：2022-09-22

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Wesley O. Mckinsey

IPC: H01L21/768 ,  H01L21/3215 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76886 ,  H01L21/32155 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/53271 ,  H01L23/535

Abstract: Methods, systems, and devices for plasma-doped trenches for memory are described. A method for forming a memory device with plasma-doped trenches may include forming a stack of materials having alternating layers of polysilicon and oxide materials. A trench may be etched in the stack and doped using a plasma doping process. In some examples, the trench may be doped by applying Boron fluoride, diborane, methane, or Boron and Carbon Hydride gases diluted with Hydrogen (H2) or Helium to the sidewalls and bottom surface of the trench, which may dope portions of the polysilicon material with Boron, Carbon, Fluorine, Helium, or Hydrogen.