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    CROSS-POINT MEMORY COMPENSATION
    11.
    发明申请
    CROSS-POINT MEMORY COMPENSATION 审中-公开

    公开(公告)号：US20200381044A1

    公开(公告)日：2020-12-03

    申请号：US16895905

    申请日：2020-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu ,  Kirk D. Prall

    IPC: G11C13/00 ,  G11C8/08

    Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

    Memory Arrays
    12.
    发明申请
    Memory Arrays 审中-公开

    公开(公告)号：US20200341105A1

    公开(公告)日：2020-10-29

    申请号：US16924068

    申请日：2020-07-08

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: G01R33/58 ,  H01L27/24 ,  G11C7/10 ,  G11C13/00 ,  G11C8/14 ,  H01L45/00 ,  G01R33/12 ,  G11C5/06 ,  G11C5/02

    Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

    Memory arrays
    13.
    发明授权
    Memory arrays 有权

    公开(公告)号：US10746835B1

    公开(公告)日：2020-08-18

    申请号：US16850293

    申请日：2020-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: G11C11/00 ,  G01R33/58 ,  G11C13/00 ,  G11C7/10 ,  H01L27/24 ,  G11C5/06 ,  H01L45/00 ,  G11C5/02 ,  G01R33/12 ,  G11C8/14 ,  G01R33/24

    Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2 F2.

    Memory Arrays
    14.
    发明授权
    Memory Arrays 有权

    公开(公告)号：US10656231B1

    公开(公告)日：2020-05-19

    申请号：US16799670

    申请日：2020-02-24

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: G11C11/00 ,  G01R33/58 ,  G11C8/14 ,  G11C13/00 ,  G11C7/10 ,  H01L27/24 ,  G11C5/02 ,  H01L45/00 ,  G01R33/12 ,  G11C5/06 ,  G01R33/24

    Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

    Integrated circuit structures comprising conductive vias and methods of forming conductive vias
    17.
    发明授权
    Integrated circuit structures comprising conductive vias and methods of forming conductive vias 有权

    公开(公告)号：US10121745B2

    公开(公告)日：2018-11-06

    申请号：US15621329

    申请日：2017-06-13

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: H01L27/24 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582

    Abstract: A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance. Integrated circuit structure comprising conductive vias independent of method of manufacture are disclosed.

    Memory Arrays
    18.
    发明申请
    Memory Arrays 审中-公开
    记忆阵列

    公开(公告)号：US20160336046A1

    公开(公告)日：2016-11-17

    申请号：US15220316

    申请日：2016-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: G11C5/02 ,  H01L45/00 ,  H01L27/24

    CPC classification number: G01R33/58 ,  G01R33/1284 ,  G01R33/24 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144

    Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2 F2.

    Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以具有沿着第一水平方向延伸的全局位线，垂直于全局位线垂直延伸的垂直局部位线以及沿垂直于第一水平方向的第二水平方向延伸的字线。 全局位线可以在第一高度级细分为第一系列，而在第二高度级可以被分为与第一高度不同的第二系列。 第一个系列的全局位线可以与第二个系列的全局位线交替。 直接在字线和垂直的局部位线之间可以存储单元格材料。 存储单元材料可以形成由字线/全局位线组合唯一地寻址的多个存储单元。 一些实施例包括具有约F2F的区域的交叉点存储单元单元。

    Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells
    20.
    发明授权
    Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells 有权

    公开(公告)号：US12167615B2

    公开(公告)日：2024-12-10

    申请号：US17589683

    申请日：2022-01-31

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: An array of vertically stacked tiers of memory cells includes horizontally oriented access lines within individual tiers of memory cells and horizontally oriented global sense lines elevationally outward of the tiers. Select transistors are elevationally inward of the tiers. Pairs of local first and second vertical lines extends through the tiers. One vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects including methods, are disclosed.

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