公开(公告)号：US20200161434A1

公开(公告)日：2020-05-21

申请号：US16688854

申请日：2019-11-19

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Isamu Asano ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/22 ,  H01L27/108 ,  G11C11/402 ,  H01L29/786

Abstract: Some embodiments include an integrated assembly having a gate material, an insulative material adjacent the gate material, and a semiconductor oxide adjacent the insulative material. The semiconductor oxide has a channel region proximate the gate material and spaced from the gate material by the insulative material. An electric field along the gate material induces carrier flow within the channel region, with the carrier flow being along a first direction. The semiconductor oxide includes a grain boundary having a portion which extends along a second direction that crosses the first direction of the carrier flow. In some embodiments, the semiconductor oxide has a grain boundary which extends along the first direction and which is offset from the insulative material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the grain boundary. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20250098213A1

公开(公告)日：2025-03-20

申请号：US18970438

申请日：2024-12-05

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L29/786 ,  H01L29/66 ,  H10B63/00

Abstract: A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. A device, a memory device, and an electronic system are also described.

公开(公告)号：US20240365546A1

公开(公告)日：2024-10-31

申请号：US18639781

申请日：2024-04-18

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: Methods, systems, and devices for multiple metal word line gates in a three dimensional (3D) memory array are described. A multi-metal control gate may be formed and used to access the memory cells. The metals may be selected such that an electric field induced in the memory cell during access is relatively even across its area. For example, metals having different work functions or resistivities may induce different electric fields. Accordingly, metals may be selected to increase an electric field induced in a planar region in the memory cell relative to if a single metal control gate were implemented such that relatively even electric fields are induced throughout the memory cell. To support formation of the multi-metal control gate, a portion of the metal forming the control gate may be partially etched and replaced with one or more other metals to form the multi-metal control gate.

公开(公告)号：US20240194264A1

公开(公告)日：2024-06-13

申请号：US18515906

申请日：2023-11-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dmitry Mikulik ,  Leo Lukose ,  Ramanathan Gandhi

IPC: G11C16/04 ,  G11C5/06 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  G11C5/063 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Memory cells, and memories and memory array structures containing such memory cells, might include a control gate, a channel, a gate dielectric between the channel and the control gate, a charge-storage node between the gate dielectric and the control gate, a charge-blocking material between the charge-storage node and the control gate, a laminated dielectric between the charge-blocking material and the control gate, and a high-K dielectric between the laminated dielectric and the control gate, wherein the laminated dielectric comprises an instance of a first dielectric material between the charge-blocking material and the high-K dielectric and an instance of a second dielectric material between the instance of the first dielectric material and the high-K dielectric, and wherein the instance of the first dielectric material has a higher oxygen areal density than an oxygen areal density of the instance of the second dielectric material.

公开(公告)号：US20230255625A1

公开(公告)日：2023-08-17

申请号：US18140757

申请日：2023-04-28

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi

IPC: A61B17/068 ,  A61B17/072 ,  A61B17/10

CPC classification number: A61B17/068 ,  A61B17/07207 ,  A61B17/105 ,  A61B2017/07271 ,  A61B2017/07278 ,  A61B2017/00473

Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230075673A1

公开(公告)日：2023-03-09

申请号：US17987779

申请日：2022-11-15

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi ,  Augusto Benvenuti ,  Giovanni Maria Paolucci

IPC: H01L29/51

Abstract: A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.

公开(公告)号：US11329133B2

公开(公告)日：2022-05-10

申请号：US16688854

申请日：2019-11-19

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Isamu Asano ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L27/108 ,  H01L29/22 ,  H01L29/786 ,  G11C11/402

Abstract: Some embodiments include an integrated assembly having a gate material, an insulative material adjacent the gate material, and a semiconductor oxide adjacent the insulative material. The semiconductor oxide has a channel region proximate the gate material and spaced from the gate material by the insulative material. An electric field along the gate material induces carrier flow within the channel region, with the carrier flow being along a first direction. The semiconductor oxide includes a grain boundary having a portion which extends along a second direction that crosses the first direction of the carrier flow. In some embodiments, the semiconductor oxide has a grain boundary which extends along the first direction and which is offset from the insulative material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the grain boundary. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210375868A1

公开(公告)日：2021-12-02

申请号：US17396049

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H01L27/105 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/24

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11152509B2

公开(公告)日：2021-10-19

申请号：US16826011

申请日：2020-03-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L27/11597 ,  H01L29/10 ,  H01L27/11514 ,  H01L29/08

Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US11107817B2

公开(公告)日：2021-08-31

申请号：US16298947

申请日：2019-03-11

Applicant: Micron Technology, inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H01L27/105 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/24

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.