公开(公告)号：US20110057267A1

公开(公告)日：2011-03-10

申请号：US12554604

申请日：2009-09-04

申请人： Harry Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

发明人： Harry Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

IPC分类号： H01L27/06 ,  H01L29/86 ,  H01L21/02 ,  H01L21/82

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0922 ,  H01L28/20 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2223/6672

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

摘要翻译： 本发明提供集成电路。 集成电路包括半导体衬底; 以及设置在半导体衬底上的无源多晶硅器件。 无源多晶硅器件还包括多晶硅特征; 以及嵌入在多晶硅特征中的多个电极。

公开(公告)号：US09190326B2

公开(公告)日：2015-11-17

申请号：US13162453

申请日：2011-06-16

申请人： Harry Hak-Lay Chuang ,  Ming Zhu

发明人： Harry Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L29/772 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/94

CPC分类号： H01L21/823437 ,  H01L29/66181 ,  H01L29/94

摘要： An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a gate structure disposed over a substrate; a source region and a drain region disposed in the substrate, wherein the gate structure interposes the source region and the drain region; and at least one post feature embedded in the gate structure.

摘要翻译： 公开了一种集成电路器件及其制造方法。 在一个示例中，集成电路器件包括设置在衬底上的栅极结构; 设置在所述基板中的源极区域和漏极区域，其中所述栅极结构插入所述源极区域和所述漏极区域; 以及嵌入在门结构中的至少一个后置特征。

公开(公告)号：US08598656B2

公开(公告)日：2013-12-03

申请号：US12719720

申请日：2010-03-08

申请人： Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang

发明人： Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/66

CPC分类号： H01L29/66484 ,  H01L21/8234 ,  H01L23/60 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region.

摘要翻译： 本公开提供了具有晶体管的半导体器件。 晶体管包括形成在半导体衬底中的源极区，漏极区和沟道区。 沟道区域设置在源区和漏区之间。 晶体管包括设置在沟道区域上的第一栅极。 晶体管包括设置在漏区上的多个第二栅极。

公开(公告)号：US08835294B2

公开(公告)日：2014-09-16

申请号：US12724984

申请日：2010-03-16

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3215 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/02697 ,  H01L21/3215 ,  H01L21/76825 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成栅极结构，所述栅极结构包括虚拟栅极，从栅极结构去除伪栅极，从而形成沟槽，形成工件 功能金属层部分地填充沟槽，形成填充沟槽的其余部分的填充金属层，执行化学机械抛光（CMP）以去除沟槽外部的金属层，并将Si，C或Ge注入剩余的 填充金属层的一部分。

公开(公告)号：US08697517B2

公开(公告)日：2014-04-15

申请号：US12724904

申请日：2010-03-16

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L21/8242

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光致抗蚀剂（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US20110230042A1

公开(公告)日：2011-09-22

申请号：US12724984

申请日：2010-03-16

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/28088 ,  H01L21/02697 ,  H01L21/3215 ,  H01L21/76825 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成栅极结构，所述栅极结构包括虚拟栅极，从栅极结构去除伪栅极，从而形成沟槽，形成工件 功能金属层部分地填充沟槽，形成填充沟槽的其余部分的填充金属层，执行化学机械抛光（CMP）以去除沟槽外部的金属层，并将Si，C或Ge注入剩余的 填充金属层的一部分。

公开(公告)号：US20110227161A1

公开(公告)日：2011-09-22

申请号：US12725081

申请日：2010-03-16

申请人： Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang

发明人： Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66484 ,  H01L21/823807 ,  H01L29/423 ,  H01L29/7391

摘要： The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底，设置在衬底上的第一栅极结构，第一栅极结构包括第一导电类型的第一栅极电极，设置在衬底上并靠近第一栅极的第二栅极结构 所述第二栅极结构包括不同于所述第一导电类型的第二导电类型的第二栅极电极，设置在所述衬底中的所述第一导电类型的第一掺杂区域，所述第一掺杂区域包括与第一导电类型对准的第一轻掺杂区域 并且第二导电类型的第二掺杂区域设置在衬底中，第二掺杂区域包括与第二栅极结构的一侧对准的第二轻掺杂区域。

公开(公告)号：US09196611B2

公开(公告)日：2015-11-24

申请号：US14250519

申请日：2014-04-11

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L31/119 ,  H01L27/06 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光刻胶（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US20140054711A1

公开(公告)日：2014-02-27

申请号：US13594289

申请日：2012-08-24

申请人： Harry Hak-Lay Chuang ,  Ming Zhu

发明人： Harry Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7391 ,  H01L21/823418 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/7889

摘要： A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed.

摘要翻译： 公开了一种半导体器件单元。 半导体器件单元包括晶体管栅极，其具有门控表面和接触表面以及与源极接触的源极区域。 半导体器件单元还包括与漏极接触接触的漏极区，其中漏极接触件不相对于晶体管栅极的选通表面与源极接触相对。 公开了其中栅极接触比漏极接触更靠近源极接触的其它半导体器件单元。

公开(公告)号：US08304831B2

公开(公告)日：2012-11-06

申请号：US12701656

申请日：2010-02-08

申请人： Ming Zhu ,  Lee-Wee Teo ,  Han-Guan Chew ,  Harry Hak-Lay Chuang

发明人： Ming Zhu ,  Lee-Wee Teo ,  Han-Guan Chew ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66659

摘要： The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.

摘要翻译： 本公开提供了具有晶体管的半导体器件。 晶体管包括衬底以及设置在衬底内的第一和第二阱。 第一和第二阱掺杂不同类型的掺杂剂。 晶体管包括至少部分地设置在第一阱上的第一栅极。 晶体管还包括设置在第二阱上的第二栅极。 晶体管还包括源区和漏区。 源极和漏极区分别设置在第一和第二阱中。 源区和漏区掺杂有相同类型的掺杂剂。