公开(公告)号：US06762448B1

公开(公告)日：2004-07-13

申请号：US10405343

申请日：2003-04-03

Applicant: Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L2708

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/66795 ,  H01L29/7842

Abstract: A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.

Abstract translation: 半导体器件包括一组翅片结构。 翅片结构的组包括导电材料，并且通过在氧化物层的开口中生长导电材料而形成。 半导体器件还包括形成在鳍片结构组的一端处的源极区域，形成在鳍片结构组的相对端处的漏极区域和至少一个栅极。

公开(公告)号：US07498225B1

公开(公告)日：2009-03-03

申请号：US11428722

申请日：2006-07-05

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02672 ,  H01L29/785

Abstract: A method for forming fin structures for a semiconductor device that includes a substrate and a dielectric layer formed on the substrate is provided. The method includes etching the dielectric layer to form a first structure, depositing an amorphous silicon layer over the first structure, and etching the amorphous silicon layer to form second and third fin structures adjacent first and second side surfaces of the first structure. The second and third fin structures may include amorphous silicon material. The method further includes depositing a metal layer on upper surfaces of the second and third fin structures, performing a metal-induced crystallization operation to convert the amorphous silicon material of the second and third fin structures to a crystalline silicon material, and removing the first structure.

Abstract translation: 提供了一种用于形成半导体器件的鳍结构的方法，该半导体器件包括衬底和形成在衬底上的电介质层。 该方法包括蚀刻介电层以形成第一结构，在第一结构上沉积非晶硅层，以及蚀刻非晶硅层以形成与第一结构的第一和第二侧表面相邻的第二和第三鳍结构。 第二和第三鳍结构可以包括非晶硅材料。 该方法还包括在第二和第三鳍结构的上表面上沉积金属层，执行金属诱导结晶操作以将第二鳍和第三鳍结构的非晶硅材料转化成晶体硅材料，并且去除第一结构 。

公开(公告)号：US07196372B1

公开(公告)日：2007-03-27

申请号：US10614177

申请日：2003-07-08

Applicant: Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

Inventor： Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

IPC: H01L29/788

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11568 ,  H01L29/785

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍，氧化物层，间隔物和一个或多个控制栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 氧化层形成在翅片上并用作存储器件的隧道氧化物。 间隔件邻近翅片的侧表面形成，并且控制栅极邻近间隔件形成。 间隔件用作非易失性存储器件的浮栅电极。

公开(公告)号：US06271563B1

公开(公告)日：2001-08-07

申请号：US09122815

申请日：1998-07-27

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L2976

CPC classification number: H01L29/66643 ,  H01L29/42376 ,  H01L29/4983

Abstract: A MOS transistor having a source and drain extension that are less than 40 nanometers in thickness to minimize the short channel effect. A gate includes a high-K dielectric spacer layer to create depletion regions in the substrate which form the drain and source extensions.

Abstract translation: 具有小于40纳米的源极和漏极延伸的MOS晶体管，以最小化短沟道效应。 栅极包括高K电介质间隔层，以在衬底中产生形成漏极和源极延伸的耗尽区。

公开(公告)号：US06200869B1

公开(公告)日：2001-03-13

申请号：US09187890

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L29/6656

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用固相杂质源。 固相杂质源可以是约300nm厚的掺杂二氧化硅层。 该结构被热退火以将来自固相杂质源的掺杂剂驱动到源区和漏区。 来自杂质源的掺杂剂提供超浅源极和漏极延伸。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US6084271A

公开(公告)日：2000-07-04

申请号：US187892

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

公开(公告)号：US07196374B1

公开(公告)日：2007-03-27

申请号：US10653274

申请日：2003-09-03

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。

公开(公告)号：US06362055B1

公开(公告)日：2002-03-26

申请号：US09144527

申请日：1998-08-31

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L218234

Abstract: A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-Si—Ge, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.

公开(公告)号：US06225661B1

公开(公告)日：2001-05-01

申请号：US09145786

申请日：1998-09-02

Applicant: Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

Inventor： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

IPC: H01L27088

CPC classification number: H01L21/28194 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/981 ,  H01L2924/00

Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

Abstract translation: 在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘 。 然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。 然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。 去除间隔物，并用栅电极材料重新填充栅极空隙。

公开(公告)号：US06190980B1

公开(公告)日：2001-02-20

申请号：US09150874

申请日：1998-09-10

Applicant: Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

Inventor： Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/26586 ,  H01L29/66492 ,  H01L29/66537

Abstract: A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in an oxide layer is defined and partially filled by insertion of nitride spacers to define an actual gate window opening. The small angle tilted implant technique has the equivalent doping effect of large angle tilted implants, and circumvents the maximum angle limit (&thgr;MAX) that occurs in the large angle implant method. The small angle tilted implant technique also automatically provides self alignment of the pocket/halo/extension implant to the gate of the device.

Abstract translation: 在ULSI致密结构中进行凹槽，晕圈和源极/漏极延伸的倾斜注入的方法。 该方法克服了在密集结构中的阴影效应，在ULSI电路中使用大角度倾斜植入技术的过程极限。 通过插入氮化物间隔物限定氧化层中的开口，并且通过插入氮化物间隔物来部分地填充以限定实际的门窗开口。 小角度倾斜植入技术具有大角度倾斜植入物的等效掺杂效应，并避开了大角度植入法中发生的最大角度限制（thetaMAX）。 小角度倾斜植入技术还自动提供袋/晕/延伸植入物到装置的门的自对准。