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    3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH ELECTRONIC CIRCUIT UNITS
    14.
    发明申请
    3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH ELECTRONIC CIRCUIT UNITS 有权

    公开(公告)号：US20230015040A1

    公开(公告)日：2023-01-19

    申请号：US17951099

    申请日：2022-09-23

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  H01L25/00

    Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus includes greater than eight pillars and less than three hundred pillars, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

    3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH AT LEAST ONE VERTICAL BUS
    15.
    发明申请
    3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH AT LEAST ONE VERTICAL BUS 有权

    公开(公告)号：US20220149012A1

    公开(公告)日：2022-05-12

    申请号：US17581977

    申请日：2022-01-24

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: A 3D device comprising: a first level comprising first transistors, said first level comprising a first interconnect; a second level comprising second transistors, said second level overlaying said first level; a third level comprising third transistors, said third level overlaying said second level; a plurality of electronic circuit units (ECUs), wherein each of said plurality of ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors, wherein each of said plurality of ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors, wherein each of said plurality of ECUs comprises a third circuit, said third circuit comprising a portion of said third transistors, wherein each of said ECUs comprises a vertical bus, wherein said vertical bus comprises greater than eight pillars and less than three hundred pillars and provides electrical connections between said first circuit and said second circuit.

    3D memory semiconductor devices and structures
    17.
    发明授权
    3D memory semiconductor devices and structures 有权

    公开(公告)号：US11069697B1

    公开(公告)日：2021-07-20

    申请号：US17235879

    申请日：2021-04-20

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: G11C16/04 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/11582 ,  H01L29/78

    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain and a channel; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel includes a circular shape or an ellipsoidal shape.

    3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS
    18.
    发明申请
    3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS 有权

    公开(公告)号：US20210151450A1

    公开(公告)日：2021-05-20

    申请号：US16649660

    申请日：2018-09-23

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

    IPC: H01L27/11556 ,  H01L23/66 ,  H01L23/538 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

    Abstract: A 3D device, the device including: at least a first level including logic circuits; at least a second level including an array of memory cells; at least a third level including special circuits; and at least a fourth level including special connectivity structures, where the special connectivity structures include one of the following: a. waveguides, or b. differential signaling, or c. radio frequency transmission lines, or d. Surface Waves Interconnect (SWI) lines, and where the third level includes Radio Frequency (“RF”) circuits to drive the special connectivity structures, where the second level overlays the first level, where the third level overlays the second level, and where the fourth level overlays the third level.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE
    19.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开

    公开(公告)号：US20200013791A1

    公开(公告)日：2020-01-09

    申请号：US16483431

    申请日：2018-02-03

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/423

    Abstract: A 3D memory device, the device including: a first vertical pillar; a second vertical pillar, where the first vertical pillar and the second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and memory control circuits, where the memory control circuits are disposed at least partially directly underneath the plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above the plurality of overlaying horizontally-oriented memory transistors.

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