公开(公告)号：US20190115340A1

公开(公告)日：2019-04-18

申请号：US15783232

申请日：2017-10-13

Applicant: NXP B.V.

Inventor： Jan Claes ,  Stephen John Sque ,  Maarten Jacobus Swanenberg ,  Da-Wei Lai

IPC: H01L27/02 ,  H01L27/07 ,  H01L29/10 ,  H01L29/735

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L27/0705 ,  H01L29/1008 ,  H01L29/735

Abstract: Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a field-effect transistor (FET) having terminals, and a common base region connected to a recombination region. The BJT and the FET are integrated with one another and include a common region that is shared by the BJT and the FET. The BJT and FET collectively bias the common base region and prevent triggering of the BJT by causing a potential of the common base region to follow a potential of one of the terminals of the BJT in response to an excessive but tolerable non-ESD voltage change at one or more of the terminals.

公开(公告)号：US10020299B2

公开(公告)日：2018-07-10

申请号：US15080154

申请日：2016-03-24

Applicant: NXP B.V.

Inventor： Da-Wei Lai

IPC: H03K5/08 ,  H01L27/02 ,  H01L29/06 ,  H03K17/081 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/7436 ,  H03K17/08108

Abstract: A silicon controlled rectifier (SCR) circuit is configured to shunt electrostatic discharge (ESD) current from a node to a reference voltage. The SCR circuit includes a first bipolar PNP transistor having a first emitter connected to the node, a first base, and a first collector. A second bipolar NPN transistor has a second collector sharing a first region with the first base, a second base sharing a second region with the first collector, and an emitter electrically connected to the reference voltage. A guard region is configured and arranged to delay triggering of the SCR circuit in response to an ESD event by impeding current flow in the second region.

公开(公告)号：US20170263599A1

公开(公告)日：2017-09-14

申请号：US15066086

申请日：2016-03-10

Applicant: NXP B.V.

Inventor： Da-Wei Lai

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/1079 ,  H01L27/027 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/73 ,  H01L29/78

Abstract: A bipolar junction transistor is configured to provide electrostatic discharge (ESD) protection for an integrated circuit. The bipolar junction transistor includes a substrate configured to function as a gate for the bipolar junction transistor. At least one drain finger extends in a first direction on a first surface of the substrate and is configured to function as a collector for the bipolar junction transistor. At least one source finger extends in the first direction on the first surface of the substrate and is configured to function as an emitter for the bipolar junction transistor. The at least one source finger includes a pickup region that is configured to set a substrate potential.

公开(公告)号：US09627372B2

公开(公告)日：2017-04-18

申请号：US15172192

申请日：2016-06-03

Applicant: NXP B.V.

Inventor： Da-Wei Lai

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/08 ,  H01L29/735

CPC classification number: H01L27/0292 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/735

Abstract: An ESD protection device for shunting an electrostatic discharge current from a first node to a second node, and an integrated circuit including the same. The device includes a first bipolar transistor having a collector and an emitter located in a first n-type region. The emitter of the first transistor is connected to the first node. The device also includes a second bipolar transistor having a collector and an emitter located in a second n-type region. The emitter of the second transistor is connected to the collector of the first bipolar transistor. The device further includes a pn junction diode including a p-type region located in a third n-type region. The p-type region of the diode is connected to the collector of the second bipolar transistor and the third n-type region is connected to the second node.

公开(公告)号：US20160372921A1

公开(公告)日：2016-12-22

申请号：US15172208

申请日：2016-06-03

Applicant: NXP B.V.

Inventor： Da-Wei Lai ,  Guido Wouter Willem Quax ,  Gijs Jan De Raad

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0285

Abstract: An electrostatic discharge power rail clamp circuit and an integrated circuit including the same. The power rail clamp circuit includes a first power rail, a second power rail and a first node. The circuit further includes an n-channel field effect transistor having a source and drain located in an isolated p-well in a semiconductor substrate. The drain is connected to the first power rail. The source and isolated p-well are connected to the first node. The circuit also includes a capacitor connected between the first node and the second power rail. The circuit further includes a resistor connected between the first power rail and the first node. The circuit also includes an inverter for controlling the gate of the field effect transistor, wherein the inverter has an input connected to the first node. The circuit further a silicon controlled rectifier connected between the first node and the second power rail.

Abstract translation: 一种静电放电电力轨钳位电路及包括该电路的集成电路。 电力轨道钳位电路包括第一电力轨道，第二电力轨道和第一节点。 该电路还包括n沟道场效应晶体管，其源极和漏极位于半导体衬底中的隔离p阱中。 漏极连接到第一个电源轨。 源和隔离p阱连接到第一个节点。 电路还包括连接在第一节点和第二电力轨道之间的电容器。 电路还包括连接在第一电源轨和第一节点之间的电阻器。 电路还包括用于控制场效应晶体管的栅极的反相器，其中反相器具有连接到第一节点的输入端。 电路还包括连接在第一节点和第二电力轨道之间的可控硅整流器。

公开(公告)号：US11133299B2

公开(公告)日：2021-09-28

申请号：US16152142

申请日：2018-10-04

Applicant: NXP B.V.

Inventor： Da-Wei Lai ,  Stephen John Sque ,  Wilhelmus Cornelis Maria Peters

IPC: H01L27/02 ,  H01L27/06 ,  H02H9/04 ,  H01L29/861 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/735

Abstract: An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.

公开(公告)号：US10475783B2

公开(公告)日：2019-11-12

申请号：US15783232

申请日：2017-10-13

Applicant: NXP B.V.

Inventor： Jan Claes ,  Stephen John Sque ,  Maarten Jacobus Swanenberg ,  Da-Wei Lai

IPC: H01L27/02 ,  H01L29/735 ,  H01L29/10 ,  H01L27/07

Abstract: Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a field-effect transistor (FET) having terminals, and a common base region connected to a recombination region. The BJT and the FET are integrated with one another and include a common region that is shared by the BJT and the FET. The BJT and FET collectively bias the common base region and prevent triggering of the BJT by causing a potential of the common base region to follow a potential of one of the terminals of the BJT in response to an excessive but tolerable non-ESD voltage change at one or more of the terminals.

公开(公告)号：US10074647B2

公开(公告)日：2018-09-11

申请号：US15013070

申请日：2016-02-02

Applicant: NXP B.V.

Inventor： Da-Wei Lai ,  Dolphin Abessolo Bidzo

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/092

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/092 ,  H02H9/046

Abstract: A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further includes a signal line connected between the first domain and the second domain. The device also includes an electrostatic discharge protection circuit for providing cross-domain ESD protection. The protection circuit includes a blocking transistor connected between the first domain power rail and the signal line. The protection circuit also includes a power rail clamp connected between the first domain power rail and the first domain ground rail. The power rail clamp is operable to apply a control signal to a gate of the blocking transistor to switch it on during normal operation and to switch it off during an ESD event. The power rail clamp is operable during the ESD event to conduct an ESD current.

公开(公告)号：US20180247928A1

公开(公告)日：2018-08-30

申请号：US15441579

申请日：2017-02-24

Applicant: NXP B.V.

Inventor： Da-Wei Lai ,  Wei-Jhih Tseng

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H01L27/0255 ,  H01L27/0259 ,  H02H9/04

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes three or more bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and a diode connected in series with the three or more bipolar transistors and one of the first and second nodes. Each of the three or more bipolar transistors includes a collector comprising collector components, an emitter comprising emitter components, and a base structure comprising a substrate region or an active region. The emitter components are alternately located with respect to the collector components. The substrate region or the active region surrounds the collector components and the emitter components. Other embodiments are also described.

公开(公告)号：US20180247927A1

公开(公告)日：2018-08-30

申请号：US15441566

申请日：2017-02-24

Applicant: NXP B.V.

Inventor： Da-Wei Lai ,  Wei-Jhih Tseng

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H02H9/04

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a first bipolar device connected to a first node, a second bipolar device connected to the first bipolar device and to a second node, and a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes. The first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure. Other embodiments are also described.