公开(公告)号：US20180191364A1

公开(公告)日：2018-07-05

申请号：US15849683

申请日：2017-12-21

Applicant: NXP B.V.

Inventor： Nenad Pavlovic

IPC: H03M1/08 ,  H03L7/099 ,  G01S7/35

CPC classification number: H03M1/0854 ,  G01S7/032 ,  G01S7/35 ,  G01S13/343 ,  H03K3/0231 ,  H03L7/099 ,  H03L7/0991 ,  H03L7/197 ,  H03L2207/06

Abstract: A digitally controlled oscillator comprising a filtering digital to analogue converter, DAC, component and a voltage controlled oscillator, VCO, component comprising at least one control terminal arranged to receive a control voltage output by the DAC component; wherein the DAC component comprises a voltage generation component arranged to generate the control voltage and at least one configurable capacitive load component to which the control voltage is applied such that a filtering bandwidth of the DAC component is configurable by way of the at least one configurable capacitive load component.

公开(公告)号：US20160238998A1

公开(公告)日：2016-08-18

申请号：US15041202

申请日：2016-02-11

Applicant: NXP B.V.

Inventor： Nenad Pavlovic ,  Vladislav Dyachenko ,  Tarik Saric

IPC: G04F10/00 ,  H03L7/099 ,  H03L7/197 ,  H03M1/38

CPC classification number: G04F10/005 ,  G01S7/02 ,  G01S7/35 ,  G01S13/32 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/1974 ,  H03L7/1976 ,  H03M1/38

Abstract: A time to digital converter (10) is disclosed. The time to digital converter (10) comprises: a synchronisation block (20) configured to output a voltage pulse (110) with duration based on a time difference between a reference oscillating signal (101) and an input oscillating signal (107); a charge pump (41) arranged to receive the voltage pulse (110) and to convert the voltage pulse into a current pulse; an integrator (50) comprising an integrator capacitor (24, 25), the integrator (50) being configured to receive the current pulse (110) and integrate the current pulse (110) as a charge on the integrator capacitor (24, 25), resulting in an integrator output voltage (115); and a successive approximation register (40) configured to determine the integrator output voltage (115) with respect to a reference voltage by adjusting the charge on the integrator capacitor (24, 25) so as to reduce the integrator output voltage (115) to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage (115) as a digital signal (125). A phase locked loop comprising the time to digital converter (10) is disclosed.

Abstract translation: 公开了一种数字转换器（10）。 数字转换器（10）的时间包括：同步块（20），被配置为基于参考振荡信号（101）和输入振荡信号（107）之间的时间差输出具有持续时间的电压脉冲（110）; 布置成接收电压脉冲（110）并将电压脉冲转换成电流脉冲的电荷泵（41）; 积分器（50），包括积分器电容器（24,25），所述积分器（50）被配置为接收所述电流脉冲（110）并且将所述电流脉冲（110）作为所述积分器电容器（24,25）上的电荷进行积分， ，导致积分器输出电压（115）; 以及逐次逼近寄存器（40），被配置为通过调整积分电容器（24,25）上的电荷来确定相对于参考电压的积分器输出电压（115），以便将积分器输出电压（115）减小到 通过逐次逼近的参考电压的最低有效位（D0），并且被配置为输出所确定的积分器输出电压（115）作为数字信号（125）。 公开了一种包括时间到数字转换器（10）的锁相环。

公开(公告)号：US20160105196A1

公开(公告)日：2016-04-14

申请号：US14512923

申请日：2014-10-13

Applicant: NXP B.V.

Inventor： Nenad Pavlovic

IPC: H03M3/00 ,  H04B1/00

CPC classification number: H03M3/322 ,  H03M1/06 ,  H03M3/368 ,  H03M3/40 ,  H03M3/422 ,  H03M3/454 ,  H03M3/464 ,  H03M3/486 ,  H03M3/494 ,  H04B1/0003

Abstract: A sigma delta receiver achieves increased stability and noise reduction. The sigma delta receiver includes a first integrator stage, an isolation stage, a second integrator stage, and a quantization stage. The first integrator stage receives an analog radio frequency (RF) signal from an antenna and generates an analog baseband signal based on the analog RF signal. The isolation stage is coupled to an output of the first integrator stage. The isolation stage receives the analog baseband signal from the first integrator stage and amplifies the analog baseband signal. The second integrator stage is coupled to an output of the isolation stage to receive the analog baseband signal. The second integrator stage further amplifies the analog baseband signal. The quantization stage converts the analog baseband signal to a digital signal, and outputs the digital signal.

Abstract translation: Σ-Δ接收器实现了增加的稳定性和降噪。 Σ-Δ接收机包括第一积分器级，隔离级，第二积分级和量化级。 第一个积分器级从天线接收模拟射频（RF）信号，并根据模拟RF信号产生模拟基带信号。 隔离级耦合到第一积分器级的输出端。 隔离级接收来自第一积分器级的模拟基带信号，并放大模拟基带信号。 第二积分器级耦合到隔离级的输出端以接收模拟基带信号。 第二个积分器级进一步放大模拟基带信号。 量化级将模拟基带信号转换为数字信号，并输出数字信号。