公开(公告)号：US10256142B2

公开(公告)日：2019-04-09

申请号：US13774350

申请日：2013-02-22

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/768 ,  H01L21/285 ,  C23C16/06 ,  H01L21/321 ,  H01L27/108 ,  C23C16/04

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

公开(公告)号：US09236297B2

公开(公告)日：2016-01-12

申请号：US14097160

申请日：2013-12-04

Applicant: Novellus Systems, Inc.

Inventor： Feng Chen ,  Raashina Humayun ,  Michal Danek ,  Anand Chandrashekar

IPC: H01L21/4763 ,  H01L21/768 ,  C23C16/02 ,  C23C16/04 ,  C23C16/14 ,  C23C16/455 ,  H01L21/285 ,  H01L21/67

CPC classification number: H01L23/535 ,  C23C16/0272 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45523 ,  C23C16/52 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.

Abstract translation: 提供了高空隙特征的无空隙钨填充的方法。 根据各种实施方案，该方法包括用钨填充特征的降温化学气相沉积（CVD）工艺。 在某些实施方案中，在化学气相沉积期间将工艺温度保持在小于约350℃以填充该特征。 降低温度的CVD钨填料提供了改进的高纵横比特征的钨填充，为氟迁移到下层提供了改进的障碍，同时获得与标准CVD填充相似的薄膜电阻率。 还提供了沉积具有低电阻率的薄钨膜的方法。 根据各种实施例，所述方法包括在沉积钨体层之前对沉积的成核层进行降低温度的低电阻率处理，和/或通过降温CVD工艺沉积体层，接着进行高温CVD工艺。

公开(公告)号：US20150056803A1

公开(公告)日：2015-02-26

申请号：US14502817

申请日：2014-09-30

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/768 ,  H01L21/3213

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32136 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76898 ,  H01L27/1052 ,  H01L27/10891

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

Abstract translation: 这里描述的是用钨和相关系统和装置填充特征的方法。 这些方法包括内向外填充技术以及特征中的共形沉积。 内向外填充技术可以包括在蚀刻钨层上的特征中的选择性沉积。 可以根据各种实施方式使用保形和非保形蚀刻技术。 本文描述的方法可用于填充垂直特征，例如钨通孔，以及水平特征，例如垂直NAND（VNAND）字线。 应用实例包括逻辑和存储器接触填充，DRAM掩埋字线填充，垂直集成存储器栅极/字线填充，以及与硅通孔（TSV）的3-D集成。

公开(公告)号：US20140162451A1

公开(公告)日：2014-06-12

申请号：US14097160

申请日：2013-12-04

Applicant: Novellus Systems, Inc.

Inventor： Feng Chen ,  Raashina Humayun ,  Michal Danek ,  Anand Chandrashekar

IPC: H01L21/768 ,  H01L21/67

CPC classification number: H01L23/535 ,  C23C16/0272 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45523 ,  C23C16/52 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.

Abstract translation: 提供了高空隙特征的无空隙钨填充的方法。 根据各种实施方案，该方法包括用钨填充特征的降温化学气相沉积（CVD）工艺。 在某些实施方案中，在化学气相沉积期间将工艺温度保持在小于约350℃以填充该特征。 降低温度的CVD钨填料提供了改进的高纵横比特征的钨填充，为氟迁移到下层提供了改进的障碍，同时获得与标准CVD填充相似的薄膜电阻率。 还提供了沉积具有低电阻率的薄钨膜的方法。 根据各种实施例，所述方法包括在沉积钨体层之前对沉积的成核层进行降低温度的低电阻率处理，和/或通过降温CVD工艺沉积体层，接着进行高温CVD工艺。

公开(公告)号：US20140069459A1

公开(公告)日：2014-03-13

申请号：US13654303

申请日：2012-10-17

Applicant: Novellus Systems, Inc.

Inventor： Yan Guan ,  Abhishek Manohar ,  Raashina Humayun ,  Panya Wongsenakhum

IPC: H05H1/24 ,  B08B9/00

CPC classification number: H05H1/24 ,  B08B9/00 ,  C11D11/0041 ,  C23C16/4405 ,  H01J37/32862

Abstract: Provided are methods and related apparatus for removing tungsten film from a station of a single-station or multi-station chamber and station component surfaces between tungsten deposition processes. In some embodiments, the methods can involve introducing an inert gas flow upstream of a gas inlet to a station and downstream of a remote plasma generator that provides activated cleaning species. In some embodiments, the methods can involve modulating inert gas flow during various stages of a cleaning process. In some embodiments, the methods can involve manipulating positions of a substrate carrier ring during various stages of the cleaning process. Also in some embodiments, the methods can involve differentially modulating the amounts of inert gas introduced to stations of a multi-station chamber. The methods can provide improved clean uniformity, reduced over-etch, and increased throughput due to shorter cleaning time.

Abstract translation: 提供了用于从钨站沉积过程中的单站或多站室和站组件表面的站去除钨膜的方法和相关装置。 在一些实施例中，所述方法可以包括将气体入口上游的惰性气体流引入到站和提供激活的清洁物质的远程等离子体发生器的下游。 在一些实施方案中，所述方法可以涉及在清洁过程的各个阶段期间调节惰性气体流。 在一些实施例中，该方法可以涉及在清洁过程的各个阶段期间操纵衬底载体环的位置。 同样在一些实施例中，该方法可以包括差分调制引入到多工位室的站的惰性气体的量。 该方法可以提供更好的清洁均匀性，减少过度蚀刻和由于较短的清洁时间而增加的生产量。

公开(公告)号：US20140017891A1

公开(公告)日：2014-01-16

申请号：US13934089

申请日：2013-07-02

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Raashina Humayun

IPC: H01L21/768

CPC classification number: H01L21/76838 ,  C23C16/14 ,  C23C16/56 ,  H01L21/28556

Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.

Abstract translation: 提供了增加钨膜的反射率以形成具有高反射率，低电阻率和低粗糙度的膜的自顶向下的方法。 这些方法涉及钨的大量沉积，然后除去沉积的钨的顶部。 在特定实施例中，去除沉积的钨的顶部部分包括使其暴露于含氟等离子体。 该方法产生具有较低粗糙度和较高反射率的低电阻率钨体层。 与常规的低电阻率钨膜相比，光滑和高反射性的钨层比光图案更容易。 应用包括形成钨线。

公开(公告)号：US20140011358A1

公开(公告)日：2014-01-09

申请号：US13928216

申请日：2013-06-26

Applicant: Novellus Systems, Inc.

Inventor： Feng Chen ,  Tsung-Han Yang ,  Juwen Gao ,  Roey Shaviv ,  Raashina Humayun ,  Deqi Wang

IPC: H01L21/285

CPC classification number: H01L21/28506 ,  C23C16/18 ,  C23C16/34 ,  C23C16/45536 ,  H01L21/28079 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53257 ,  H01L29/45 ,  H01L29/495 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods, apparatus, and systems for depositing tensile or compressive tungsten films are described. In one aspect, a method includes providing a substrate to a chamber. The substrate has a field region and a feature recessed from the field region. Then, the substrate is exposed to an organometallic tungsten precursor. The organometallic tungsten precursor not adsorbed onto the substrate is removed from the chamber. The substrate is treated with a first treatment including a heat treatment or a plasma treatment to form a tungsten layer on the substrate. After treating the substrate, residual gasses are removed from the chamber. The tungsten layer on the substrate is treated with a second treatment including a heat treatment or a plasma treatment.

Abstract translation: 描述了用于沉积拉伸或压缩钨膜的方法，装置和系统。 一方面，一种方法包括向腔室提供衬底。 衬底具有场区域和从场区域凹陷的特征。 然后，将基板暴露于有机金属钨前体。 未吸附到基底上的有机金属钨前体从腔室中除去。 用包括热处理或等离子体处理在内的第一处理来处理衬底，以在衬底上形成钨层。 处理基板后，从室中除去残留的气体。 用包括热处理或等离子体处理的第二处理来处理衬底上的钨层。

公开(公告)号：US09673146B2

公开(公告)日：2017-06-06

申请号：US14989444

申请日：2016-01-06

Applicant: Novellus Systems, Inc.

Inventor： Feng Chen ,  Raashina Humayun ,  Michal Danek ,  Anand Chandrashekar

IPC: H01L21/44 ,  H01L23/535 ,  C23C16/02 ,  C23C16/04 ,  C23C16/14 ,  C23C16/455 ,  H01L21/285 ,  H01L21/768 ,  H01L21/67 ,  C23C16/52 ,  H01L23/532

CPC classification number: H01L23/535 ,  C23C16/0272 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45523 ,  C23C16/52 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.

公开(公告)号：US09653353B2

公开(公告)日：2017-05-16

申请号：US13851885

申请日：2013-03-27

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/285 ,  H01L27/105 ,  H01L27/108 ,  C23C16/04 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32136 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76898 ,  H01L27/1052 ,  H01L27/10891

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

公开(公告)号：US09240347B2

公开(公告)日：2016-01-19

申请号：US14502817

申请日：2014-09-30

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/285 ,  H01L27/105 ,  H01L27/108 ,  C23C16/04 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32136 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76898 ,  H01L27/1052 ,  H01L27/10891

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

Abstract translation: 这里描述的是用钨和相关系统和装置填充特征的方法。 这些方法包括内向外填充技术以及特征中的共形沉积。 内向外填充技术可以包括在蚀刻钨层上的特征中的选择性沉积。 可以根据各种实施方式使用保形和非保形蚀刻技术。 本文描述的方法可用于填充垂直特征，例如钨通孔，以及水平特征，例如垂直NAND（VNAND）字线。 应用实例包括逻辑和存储器接触填充，DRAM掩埋字线填充，垂直集成存储器栅极/字线填充，以及与硅通孔（TSV）的3-D集成。