-
公开(公告)号：US10757357B2
公开(公告)日：2020-08-25
申请号：US16442666
申请日：2019-06-17
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Shuzo Hiraide , Masato Osawa , Satoru Adachi
Abstract: An imaging element includes: a plurality of pixels where each pixel is configured to generate an imaging signal; a noise eliminating circuit configured to eliminate a noise component included in the imaging signal; a plurality of column source follower buffers where each column source follower buffer is configured to amplify the imaging signal from which the noise component has been eliminated by the noise eliminating circuit, and output the amplified signal; a horizontal scanning circuit configured to sequentially select the column source follower buffer and output the imaging signal; and a buffer circuit which is connected with the column source follower buffer sequentially selected by the horizontal scanning circuit to form a voltage follower circuit, the buffer circuit being configured to perform impedance conversion on a voltage of the imaging signal output from the column source follower buffer, and output the converted signal to an outside.
-
公开(公告)号：US10277845B2
公开(公告)日：2019-04-30
申请号：US15902014
申请日：2018-02-22
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Masato Osawa
Abstract: There is provided a method of driving a solid-state imaging device, the solid-state imaging device including a plurality of column circuits which are arranged for each column of pixels and an amplification and selection circuit configured to amplify a differential signal based on a column pixel signal and a column reset signal, the method including causing the amplification and selection circuit to perform at least two operations among a first operation of sampling the column pixel signal, a second operation of sampling the column reset signal, and a third operation of output the amplified differential signal in parallel in the same period; and causing components connected to different horizontal signal lines to perform operations corresponding to the first to third operation in that order, and causing the components to perform different operations in parallel in the same period with respect to the first to third operations.
-
公开(公告)号：US20180062595A1
公开(公告)日：2018-03-01
申请号：US15788505
申请日：2017-10-19
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Yasunari Harada , Hideki Kato
CPC classification number: H03F3/72 , H03F1/26 , H03F3/45475 , H03F2200/135 , H03F2200/213 , H03F2200/411 , H03F2200/45 , H03F2203/45514 , H03F2203/45551 , H03F2203/7231 , H03G1/0094 , H03G3/001 , H03M1/1245
Abstract: In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain.
-
公开(公告)号：US20150333715A1
公开(公告)日：2015-11-19
申请号：US14810853
申请日：2015-07-28
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada
IPC: H03F3/45
CPC classification number: H03F3/45179 , H03F3/45197 , H03F2200/261 , H03F2203/45026
Abstract: An instrumentation amplifier includes: a first input stage configured to shift a level of a first input voltage applied to a first input terminal and to output the level-shifted voltage; a second input stage configured to shift a level of a second input voltage applied to a second input terminal and to output the level-shifted voltage; a first resistor configured to generate a differential current corresponding to a difference between the voltage output from the first input stage and the voltage output from the second input stage; a second resistor configured to convert the differential current into a first output voltage; a third resistor configured to convert the differential current into a second output voltage; a first output stage configured to output the first output voltage from a first output terminal; and a second output stage configured to output the second output voltage from a second output terminal.
Abstract translation: 仪表放大器包括：第一输入级，被配置为移位施加到第一输入端的第一输入电压的电平并输出电平移位电压; 第二输入级，被配置为移位施加到第二输入端的第二输入电压的电平并输出电平移位电压; 第一电阻器，被配置为产生对应于从第一输入级输出的电压与从第二输入级输出的电压之间的差的差分电流; 第二电阻器，被配置为将所述差分电流转换为第一输出电压; 第三电阻器，被配置为将所述差分电流转换为第二输出电压; 第一输出级，被配置为从第一输出端子输出第一输出电压; 以及第二输出级，被配置为从第二输出端子输出第二输出电压。
-
公开(公告)号：US10700697B2
公开(公告)日：2020-06-30
申请号：US15998842
申请日：2018-08-17
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Yasunari Harada , Shuzo Hiraide , Hideki Kato
Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.
-
Patent Agency Ranking
公开(公告)号：US10601436B2
公开(公告)日：2020-03-24
申请号：US16415067
申请日：2019-05-17
Applicant: OLYMPUS CORPORATION
Inventor： Shuzo Hiraide , Yasunari Harada , Masato Osawa
Abstract: A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.
-
公开(公告)号：US10516410B2
公开(公告)日：2019-12-24
申请号：US16100534
申请日：2018-08-10
Applicant: OLYMPUS CORPORATION
Inventor： Shuzo Hiraide , Yasunari Harada , Masato Osawa , Hideki Kato
IPC: H03M1/46 , H01G4/012 , H01L23/522 , H01G4/38 , H01G4/40
Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.
-
公开(公告)号：US10297626B2
公开(公告)日：2019-05-21
申请号：US15794474
申请日：2017-10-26
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Masato Osawa
Abstract: A semiconductor device includes a pixel array, a plurality of column circuits, an amplifier, switch arrays of a first layer to an nth layer, and signal lines of the first layer to the nth layer. n is an integer of two or more. The switch array of an ith layer is disposed between the switch array of an (i+1)th layer and the amplifier. i is an integer of one or more and less than n. The signal line of the first layer is connected to the nth amplifier. The signal line of the nth layer is connected to the switch array of the nth layer. Each of the plurality of switches included in the switch array of the nth layer is connected to the column circuit.
-
公开(公告)号：US10277237B2
公开(公告)日：2019-04-30
申请号：US16043920
申请日：2018-07-24
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Shuzo Hiraide , Masato Osawa , Hideki Kato
Abstract: A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal.
-
公开(公告)号：US20180351568A1
公开(公告)日：2018-12-06
申请号：US16100534
申请日：2018-08-10
Applicant: OLYMPUS CORPORATION
Inventor： Shuzo Hiraide , Yasunari Harada , Masato Osawa , Hideki Kato
IPC: H03M1/46 , H01G4/012 , H01G4/38 , H01L23/522
CPC classification number: H03M1/46 , H01G4/012 , H01G4/38 , H01G4/40 , H01L23/5223 , H01L23/5225 , H03M1/466
Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.
-
-
-
-
-
-
-
-
-
Search Results
25
records
(took 0.018 seconds)
