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    IMAGE SENSOR FAR END DRIVER CIRCUITRY PROVIDING FAST SETTLING ROW CONTROL SIGNALS
    12.
    发明申请
    IMAGE SENSOR FAR END DRIVER CIRCUITRY PROVIDING FAST SETTLING ROW CONTROL SIGNALS 有权

    公开(公告)号：US20210152756A1

    公开(公告)日：2021-05-20

    申请号：US16685663

    申请日：2019-11-15

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Rui Wang ,  Hiroaki Ebihara ,  Zhiyong Zhan ,  Liang Zuo ,  Min Qu ,  Wanqing Xin ,  Xuelian Liu

    IPC: H04N5/341 ,  H04N5/351 ,  H04N5/378

    Abstract: An image sensor includes a pixel array with rows and columns of pixels. Each row of the pixel array has a first end that is opposite a second end of each row of the pixel array. Control circuitry is coupled to the first end of each row of the pixel array to provide control signals to each row of the pixel array from the first end of each row of the pixel array. Far end driver circuitry coupled to the second end of each row of the pixel array to selectively further drive from the second end of each row of the pixel array the control signals provided by the control circuitry from the first end of each row of the pixel array. The control circuitry is further coupled to provide far end control signals to the far end driver circuitry.

    Bitline settling improvement and FPN reduction by floating bitline during charge transfer
    13.
    发明授权
    Bitline settling improvement and FPN reduction by floating bitline during charge transfer 有权

    公开(公告)号：US10290673B1

    公开(公告)日：2019-05-14

    申请号：US15853463

    申请日：2017-12-22

    Applicant: OmniVision Technologies, Inc.

    Inventor： Rui Wang ,  Min Qu ,  Hiroaki Ebihara ,  Zhiyong Zhan

    IPC: H04N5/222 ,  H01L27/146 ,  H04N5/378 ,  H04N5/235 ,  H04N5/374

    Abstract: A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator. A current source generator is coupled between the bitline source node and a ground. The current source generator provides adjustable current to the bitline source node through a bias transistor controlled by a bias control voltage.

    READOUT CIRCUITRY FOR IMAGE SENSOR
    15.
    发明申请
    READOUT CIRCUITRY FOR IMAGE SENSOR 有权
    图像传感器读出电路

    公开(公告)号：US20160316164A1

    公开(公告)日：2016-10-27

    申请号：US14696120

    申请日：2015-04-24

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Jie Shen ,  Min Qu ,  Hyunseok Lee

    IPC: H04N5/378 ,  H04N5/374

    CPC classification number: H04N5/378 ,  H04N5/374

    Abstract: Readout circuitry to readout an array of image sensor pixels includes readout units that include a plurality of analog-to-digital converters (“ADCs”), a plurality of blocks of Static Random-Access Memory (“SRAM”), and a plurality of blocks of Dynamic Random-Access Memory (“DRAM”). The plurality ADCs is coupled to readout analog image signals two-dimensional blocks of the array of image sensor pixels. The plurality of blocks of SRAM is coupled to receive digital image signals from the ADCs. The digital image signals are representative of the analog image signal readout from the two-dimensional block of pixels. The plurality of blocks of DRAM is coupled to the blocks of SRAM. Each block of SRAM is coupled to sequentially output the digital image signals to each of the blocks of DRAM. Each of the readout units are coupled to output the digital image signals as a plurality of Input/Output (“IO”) signals.

    Abstract translation: 用于读出图像传感器像素阵列的读出电路包括：读出单元，其包括多个模数转换器（“ADC”），多个静态随机存取存储器块（“SRAM”），以及多个 动态随机存取存储器块（“DRAM”）。 多个ADC耦合到图像传感器像素阵列的读出模拟图像信号二维块。 多个SRAM块被耦合以从ADC接收数字图像信号。 数字图像信号表示从二维像素块读出的模拟图像信号。 DRAM的多个块耦合到SRAM块。 SRAM的每个块被耦合以顺序地将数字图像信号输出到DRAM的每个块。 每个读出单元被耦合以输出数字图像信号作为多个输入/输出（“IO”）信号。

    Circuit and method for image artifact reduction in high-density, highpixel-count, image sensor with phase detection autofocus
    17.
    发明授权
    Circuit and method for image artifact reduction in high-density, highpixel-count, image sensor with phase detection autofocus 有权

    公开(公告)号：US11683604B1

    公开(公告)日：2023-06-20

    申请号：US17678533

    申请日：2022-02-23

    Applicant: OmniVision Technologies, Inc.

    Inventor： Liang Zuo ,  Rui Wang ,  Selcuk Sen ,  Xuelian Liu ,  Min Qu ,  Hiroaki Ebihara

    IPC: H04N25/704 ,  H04N25/11 ,  H04N25/60

    CPC classification number: H04N25/704 ,  H04N25/11 ,  H04N25/60

    Abstract: An image sensor includes an array of multiple-photodiode cells, each photodiode coupled through a selection transistor to a floating diffusion of the cell, the selection transistors controlled by respective transfer lines, a reset, a sense source follower, and a read transistor coupled from the source follower to a data line. The array includes phase detection rows with phase detection cells and normal cells; and a compensation row of more cells. In embodiments, each phase detection row has cells with at least one photodiode coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the row. In embodiments, the compensation row has cells with photodiodes coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the compensation row.

    Ramp generator providing high resolution fine gain including fractional divider with delta-sigma modulator
    18.
    发明授权
    Ramp generator providing high resolution fine gain including fractional divider with delta-sigma modulator 有权

    公开(公告)号：US11595030B2

    公开(公告)日：2023-02-28

    申请号：US16867399

    申请日：2020-05-05

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Lihang Fan ,  Liang Zuo ,  Nijun Jiang ,  Min Qu ,  Xuelian Liu

    IPC: H03K4/06 ,  H04N5/378 ,  H03M1/56 ,  H03M3/00

    Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

    Image sensor with frame level black level calibration
    19.
    发明授权
    Image sensor with frame level black level calibration 有权

    公开(公告)号：US11206392B1

    公开(公告)日：2021-12-21

    申请号：US16931194

    申请日：2020-07-16

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Liang Zuo ,  Min Qu ,  Xuelian Liu ,  Rui Wang ,  Zhe Gao ,  Zhiyong Zhan

    IPC: H04N17/00 ,  H04N5/3745 ,  H04N5/378

    Abstract: An image sensor includes a pixel array with active rows of pixel cells, a black level calibration row with black image data generation circuits coupled to generate black image data signals representative of an absence of the incident light, and a dummy row with black level clamping circuits coupled to receive a black sun reference voltage to clamp bitlines of the pixel array, and a black level calibration circuit coupled to receive the black sun reference voltage to generate a black sun calibration voltage. A black sun feedback circuit is coupled to generate the black sun reference voltage in response to the black sun calibration voltage and a black level sample reference, and a black level sampling circuit is coupled to the bitlines to sample the black image data signals to generate the black level sample reference received by the black sun feedback circuit.

    Circuit and method for control of counter start time
    20.
    发明授权
    Circuit and method for control of counter start time 有权

    公开(公告)号：US11128307B2

    公开(公告)日：2021-09-21

    申请号：US16175586

    申请日：2018-10-30

    Applicant: OmniVision Technologies, Inc.

    Inventor： Rui Wang ,  Yu-Shen Yang ,  Shan Chen ,  Min Qu

    IPC: H03M1/00 ,  H03M1/06 ,  H04N5/361 ,  H04N5/376 ,  H04N5/369 ,  H04N5/378

    Abstract: An analog to digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps towards the starting voltage. A counter circuit is coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline. In response to the ramp signal equaling the pixel signal voltage, the comparator stops the counter.

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