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182 条记录 (耗时 0.018 秒)

    Methods of forming inductors on integrated circuits
    15.
    发明授权
    Methods of forming inductors on integrated circuits 有权
    在集成电路上形成电感器的方法

    公开(公告)号：US08042260B2

    公开(公告)日：2011-10-25

    申请号：US12250385

    申请日：2008-10-13

    申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

    发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

    IPC分类号： H01F7/06

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

    摘要： The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.

    摘要翻译： 所要求保护的发明涉及在半导体衬底上形成一个或多个电感器的方法。 在一个实施例中，公开了一种在包括集成电路的半导体衬底上形成电感器芯元件阵列的方法。 第一组间隔开的金属芯元件形成在衬底上。 然后在芯元件的侧表面上形成隔离侧壁。 之后，在衬底上形成第二组金属芯元件。 第一和第二组芯元件基本上是共面的和交错的，使得只有隔离侧壁分隔相邻的芯元件。 具体实施例涉及其他处理操作，例如不同类型的金属的选择性电镀以形成核心元件和/或沉积和蚀刻离开隔离层以在核心元件上形成隔离侧壁。

    CMOS COMPATIBLE INTEGRATED HIGH DENSITY CAPACITOR STRUCTURE AND PROCESS SEQUENCE
    17.
    发明申请
    CMOS COMPATIBLE INTEGRATED HIGH DENSITY CAPACITOR STRUCTURE AND PROCESS SEQUENCE 审中-公开
    CMOS兼容一体化高密度电容器结构和工艺顺序

    公开(公告)号：US20100079929A1

    公开(公告)日：2010-04-01

    申请号：US12243123

    申请日：2008-10-01

    申请人： Peter Smeys ,  Peter Johnson

    发明人： Peter Smeys ,  Peter Johnson

    IPC分类号： H01G9/07 ,  H01G9/00

    CPC分类号： H01G9/15 ,  H01G9/0032 ,  H01L21/02183 ,  H01L21/02258 ,  H01L21/31687 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/40

    摘要： Integrated circuits structures and process sequences are provided for forming CMOS compatible high-density capacitors. The anodization of tantalum to tantalum oxide in the formation of the inter-plate capacitor dielectric results in very high dielectric constants since the defects usually found in the inter-plate dielectric are eliminated in the volume expansion that occurs during the oxidation of the tantalum material. This permits the fabrication of larger capacitors that can be incorporated into standard CMOS process flows.

    摘要翻译： 集成电路结构和工艺顺序被提供用于形成CMOS兼容的高密度电容器。 在形成板间电容器电介质中，钽到氧化钽的阳极氧化导致非常高的介电常数，因为在钽材料的氧化期间发生的体积膨胀中消除了在板间电介质中通常发现的缺陷。 这允许制造可并入标准CMOS工艺流程的较大电容器。

    Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method
    20.
    发明授权
    Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method 有权
    功率晶体管具有改善的高端工作特性和降低电阻及相关设备和方法

    公开(公告)号：US08274129B2

    公开(公告)日：2012-09-25

    申请号：US12589491

    申请日：2009-10-23

    申请人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

    发明人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

    IPC分类号： H01L23/58

    CPC分类号： H01L29/7835 ,  H01L21/76898 ,  H01L29/407 ,  H01L29/66659

    摘要： A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.

    摘要翻译： 一种方法包括在绝缘体上半导体结构的第一侧上形成晶体管器件。 绝缘体上半导体结构包括衬底，电介质层和衬底和电介质层之间的掩埋层。 该方法还包括通过绝缘体上半导体结构形成导电插塞。 导电插头与晶体管器件电连接。 该方法还包括在绝缘体上半导体结构的第二侧上形成场板，其中场板与导电插头电连接。 晶体管器件可以具有至少600V的击穿电压，并且场板可以沿着晶体管器件的长度的至少40％延伸。