公开(公告)号：US06480068B1

公开(公告)日：2002-11-12

申请号：US09966055

申请日：2001-09-28

Applicant: Fernando A. Mujica ,  Prakash Easwaran ,  Sandeep Kesrimal Oswal

Inventor： Fernando A. Mujica ,  Prakash Easwaran ,  Sandeep Kesrimal Oswal

IPC: H03G310

CPC classification number: H03G3/3042

Abstract: The present invention provides a hardware assisted automatic gain control (AGC) for a communication network. A dedicated hardware portion of the AGC, which works in cooperation with software implemented functionality (400), is included to detect saturation conditions in the internal nodes of the analog front end (200) in which a plurality of gain stages (PGA1, PGA2, PGA3) and filter stages (H1, H2, H3) are interleaved with inaccessible intermediate points. The saturation detection logic includes a comparator (21, 22, 23) and flip-flop (27, 28, 29) for each gain stage (PGA1, PGA2, PGA3) and can be integrated directly in the analog front end 200. The dedicated hardware can further be included in a codec of a modem in a digital subscriber line (DSL) system.

Abstract translation: 本发明提供了一种用于通信网络的硬件辅助自动增益控制（AGC）。 包括与软件实现的功能（400）协同工作的AGC的专用硬件部分，以检测模拟前端（200）的内部节点中的饱和状态，其中多个增益级（PGA1，PGA2， PGA3）和滤波器级（H1，H2，H3）与不可访问的中间点交错。 饱和检测逻辑包括用于每个增益级（PGA1，PGA2，PGA3）的比较器（21,22,23）和触发器（27,28,29），并且可以直接集成在模拟前端200中。专用 硬件可以进一步包括在数字用户线（DSL）系统中的调制解调器的编解码器中。

公开(公告)号：US08912843B2

公开(公告)日：2014-12-16

申请号：US13009868

申请日：2011-01-20

Applicant: Prasun Kali Bhattacharyya ,  Sumanth Chakkirala ,  Prakash Easwaran

Inventor： Prasun Kali Bhattacharyya ,  Sumanth Chakkirala ,  Prakash Easwaran

IPC: H04B1/10 ,  H03H7/01 ,  H03H7/06 ,  H03H11/12

CPC classification number: H03H7/0153 ,  H03H7/06 ,  H03H11/12 ,  H03H2210/012 ,  H03H2210/028

Abstract: An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.

Abstract translation: 超低截止频率滤波器。 滤波电路包括响应于输入信号和反馈信号的控制电路以产生控制信号。 滤波器电路包括耦合到控制电路的可控电阻器。 可控电阻响应于参考信号和控制信号以产生反馈信号。 滤波器电路包括耦合到控制电路和可控电阻器的反馈路径，以将来自可控电阻器的反馈信号耦合到控制电路，从而从输入信号和参考信号中的至少一个消除噪声，并且防止电压误差 在滤波电路中。

公开(公告)号：US20130307502A1

公开(公告)日：2013-11-21

申请号：US13472461

申请日：2012-05-15

Applicant: Prasun Kali Bhattacharyya ,  Prakash Easwaran

Inventor： Prasun Kali Bhattacharyya ,  Prakash Easwaran

IPC: G05F1/10

CPC classification number: G05F1/565 ,  G05F1/575

Abstract: A voltage regulator includes an amplifier, a first buffer and a second buffer. The amplifier is designed to generate an error voltage between a reference voltage and a voltage at an output node of the voltage regulator. The first buffer is coupled to receive the amplified error voltage and, in response, to drive a first pass transistor. The first buffer includes a non-linear resistance element. The resistance of the non-linear resistance element varies non-linearly with a load current drawn from the output node. The second buffer is coupled to receive the amplified error voltage, and in response, to drive a second pass transistor. The second buffer includes a linear resistance element. The resistance of the linear element is a constant. The use of the non-linear resistance element enables reduction in power consumption in the voltage regulator.

Abstract translation: 电压调节器包括放大器，第一缓冲器和第二缓冲器。 放大器设计用于在电压调节器的输出节点处产生参考电压和电压之间的误差电压。 第一缓冲器被耦合以接收放大的误差电压，并且作为响应来驱动第一传输晶体管。 第一缓冲器包括非线性电阻元件。 非线性电阻元件的电阻随从输出节点引出的负载电流而非线性变化。 第二缓冲器被耦合以接收放大的误差电压，并且响应于驱动第二传输晶体管。 第二缓冲器包括线性电阻元件。 线性元件的电阻是一个常数。 使用非线性电阻元件能够降低电压调节器的功耗。

公开(公告)号：US20120193989A1

公开(公告)日：2012-08-02

申请号：US13071533

申请日：2011-03-25

Applicant: Prakash Easwaran ,  Saumitra Singh ,  Rupak Ghayal ,  Amit Premy

Inventor： Prakash Easwaran ,  Saumitra Singh ,  Rupak Ghayal ,  Amit Premy

IPC: H02J3/04

CPC classification number: G05F1/67 ,  Y10T307/685

Abstract: In a solar panel array that includes a string of series-connected panels, the load current flowing through the string is measured. The peak current (Ipp) of a panel in the string is determined. A current equal to the difference of the load current and the peak current (Ipp) is generated in a current source connected across the output terminals of the panel. The panel is thereby operated at its maximum power point (MPP). To determine the peak current (Ipp) of the panel, the magnitude of current flowing through the panel is iteratively changed and the corresponding power generated by the panel is computed. The change in the current through the panel and the measurement of the corresponding power are repeated until a maximum power is determined as being generated by the panel. The maximum power corresponds to the maximum power point (MPP) and the peak current (Ipp) of the panel.

Abstract translation: 在包括一系列串联连接的面板的太阳能电池板阵列中，测量流过该串的负载电流。 确定字符串中面板的峰值电流（Ipp）。 在连接在面板的输出端子上的电流源中产生等于负载电流和峰值电流（Ipp）差的电流。 因此，面板以其最大功率点（MPP）运行。 为了确定面板的峰值电流（Ipp），流过面板的电流的大小被迭代地改变，并且计算面板产生的对应的功率。 重复通过面板的电流的变化和对应的功率的测量，直到最大功率被确定为由面板产生。 最大功率对应于面板的最大功率点（MPP）和峰值电流（Ipp）。

公开(公告)号：US07327997B2

公开(公告)日：2008-02-05

申请号：US10711724

申请日：2004-09-30

Applicant: Gaurav Chandra ,  Preetam Charan Anand Tadeparthy ,  Prakash Easwaran

Inventor： Gaurav Chandra ,  Preetam Charan Anand Tadeparthy ,  Prakash Easwaran

IPC: H04B1/10

CPC classification number: H03H11/126 ,  H04B1/16

Abstract: A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor, a second resistor, and a second capacitor. The second capacitor is connected in parallel between the inverting input terminal and an output path of the operational amplifier. The second resistor is connected between the output terminal of the operational amplifier and a second node on a path connecting the input signal to the inverting input terminal. The first resistor is coupled between the first node and inverting input terminal of the operational amplifier. The first capacitor is coupled between the first node and Vss. Due to such connections, the filter circuit operates as a second order filter circuit, thereby providing a desired high level of filtering. Also, as the filter circuit is implemented with a single operational amplifier, the power and area requirements are reduced.

Abstract translation: 根据本发明一方面提供的跨阻抗滤波器电路包括运算放大器，第一电阻器，第一电容器，第二电阻器和第二电容器。 第二电容器并联连接在反相输入端和运算放大器的输出路径之间。 第二电阻器连接在运算放大器的输出端和将输入信号连接到反相输入端的路径上的第二节点之间。 第一电阻耦合在运算放大器的第一节点和反相输入端之间。 第一电容器耦合在第一节点和Vss之间。 由于这种连接，滤波器电路作为二阶滤波器电路工作，从而提供期望的高级滤波。 而且，由于滤波器电路由单个运算放大器实现，所以功率和面积要求降低。

公开(公告)号：US20070205834A1

公开(公告)日：2007-09-06

申请号：US11366006

申请日：2006-02-28

Applicant: Prakash Easwaran ,  Anant Kamath ,  Rupak Ghayal ,  Birman Chattopadhyay ,  Gopal Nayak ,  Sameer Joshi ,  Mithun Neelakant ,  Subhash Pai ,  Shivaprakash Halagur

Inventor： Prakash Easwaran ,  Anant Kamath ,  Rupak Ghayal ,  Birman Chattopadhyay ,  Gopal Nayak ,  Sameer Joshi ,  Mithun Neelakant ,  Subhash Pai ,  Shivaprakash Halagur

IPC: H03L7/00

CPC classification number: H03L7/093 ,  E05Y2400/30 ,  H03L7/099 ,  H03L7/189

Abstract: Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes at least two control signals. One of the control signals is provided by a circuit that is susceptible to drift. This control signal is provided both to a systems or device under control, and to a detection circuit. The detection circuit is operable to detect a drift in the control signal. In addition, the detection circuit provides another control signal that varies as a function of the drift in the received control signal.

Abstract translation: 公开了用于漂移补偿的各种系统和方法。 作为一个示例，公开了一种用于补偿控制电路中的漂移的系统，其包括至少两个控制信号。 控制信号之一由容易漂移的电路提供。 该控制信号被提供给被控制的系统或设备，以及检测电路。 检测电路可操作以检测控制信号中的漂移。 此外，检测电路提供另一控制信号，该控制信号根据所接收的控制信号中的漂移而变化。

公开(公告)号：US06983032B2

公开(公告)日：2006-01-03

申请号：US09941002

申请日：2001-08-28

Applicant: Fernando A. Mujica ,  Udayan Dasgupta ,  Sandeep Kesrimal Oswal ,  Murtaza Ali ,  Pradeep Kiran Sarvepalli ,  Prakash Easwaran ,  Diptendra Narayan Basu

Inventor： Fernando A. Mujica ,  Udayan Dasgupta ,  Sandeep Kesrimal Oswal ,  Murtaza Ali ,  Pradeep Kiran Sarvepalli ,  Prakash Easwaran ,  Diptendra Narayan Basu

IPC: H03D3/24

CPC classification number: H04L7/0337 ,  H04L27/2657

Abstract: The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).

Abstract translation: 本发明提供了一种在本地时钟信号与通信网络中的远程时钟信号同步的装置，系统和方法。 相位信息用于计算在本地生成的时钟与远程时钟同步所需的每单位时间的“时钟抖动”数量。 在本地时钟信号的特定点引入（去除）给定量的延迟会导致正（负）抖动，其中最小值定义抖动分辨率。 响应于由相位误差模块（520）发出的定时校正信号，从由相位选择器（350）选择的多个抽头延迟线元件（310）中将抖动引入本地时钟信号。

公开(公告)号：US06914546B2

公开(公告)日：2005-07-05

申请号：US10837092

申请日：2004-04-29

Applicant: Prakash Easwaran ,  Mrinal Das

Inventor： Prakash Easwaran ,  Mrinal Das

IPC: H03M1/18 ,  H03M3/00 ,  H03M7/38 ,  H04B1/38

CPC classification number: H03M7/3015 ,  H03M7/3026 ,  H03M7/304

Abstract: A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set of step coefficients (GP2, GP4) are utilized to determined the step size and thereby the overall gain of the modulator (350). A feedback path is provided and configured to deliver the output of the modulator to a gain control block (355) which provides control and stability across the entire transmission bandwidth. A multilevel digital output (320) is provided which represents levels of signal in the digital domain and reduces the number of discrete components required to achieve a particular amount of gain.

Abstract translation: 可以在调制解调器（120）的数模（DAC）部分（144）中使用Σ-Δ调制器（350）以实现期望的增益编程级别。 利用一组步进系数（GP2，GP4）来确定步长，从而确定调制器（350）的整体增益。 反馈路径被提供和配置为将调制器的输出传递到增益控制块（355），增益控制块（355）在整个传输带宽上提供控制和稳定性。 提供了多级数字输出（320），其表示数字域中的信号电平，并且减少了实现特定增益量所需的离散组件的数量。

公开(公告)号：US09285816B2

公开(公告)日：2016-03-15

申请号：US13071531

申请日：2011-03-25

Applicant: Prakash Easwaran ,  Saumitra Singh ,  Rupak Ghayal ,  Amit Premy

Inventor： Prakash Easwaran ,  Saumitra Singh ,  Rupak Ghayal ,  Amit Premy

IPC: G01J1/20 ,  G05F1/67 ,  H01L31/05 ,  H02S50/10 ,  H02J3/38

CPC classification number: G05F1/67 ,  H01L31/05 ,  H01L31/0504 ,  H02J3/385 ,  H02S50/10 ,  Y02E10/50 ,  Y02E10/58 ,  Y10T307/609 ,  Y10T307/685

Abstract: In a solar panel array, each solar panel in a series-connected string has a current source connected across its output terminals. The current source generates a programmable output current equal to the difference of the load current drawn from the panel and the current corresponding to the maximum power point (MPP) of the panel. As a result, each of the panels in the string is operated at its MPP. When the array contains multiple strings connected in parallel, a voltage source is additionally connected in series with each string. The voltage sources are programmable to generate corresponding output voltages to enable operation of each panel in each of the multiple strings at its MPP. Respective control blocks providing the current sources and voltage sources automatically determine the MPP of the corresponding panels. In an embodiment, the control blocks are implemented as DC-DC converters in conjunction with measurement and communication units.

Abstract translation: 在太阳能电池板阵列中，串联串联的每个太阳能电池板具有连接在其输出端子上的电流源。 电流源产生等于从面板吸取的负载电流与对应于面板最大功率点（MPP）的电流的差值的可编程输出电流。 结果，串中的每个面板在其MPP上操作。 当阵列包含并联连接的多个串时，电压源与每个串串连接。 电压源是可编程的，以产生相应的输出电压，以使其在MPP中的多个串中的每一个中能够操作每个面板。 提供电流源和电压源的各个控制块自动确定相应面板的MPP。 在一个实施例中，控制块与测量和通信单元一起被实现为DC-DC转换器。

公开(公告)号：US08618693B2

公开(公告)日：2013-12-31

申请号：US13071533

申请日：2011-03-25

Applicant: Prakash Easwaran ,  Saumitra Singh ,  Rupak Ghayal ,  Amit Premy

Inventor： Prakash Easwaran ,  Saumitra Singh ,  Rupak Ghayal ,  Amit Premy

IPC: H02J1/00

CPC classification number: G05F1/67 ,  Y10T307/685

Abstract: In a solar panel array that includes a string of series-connected panels, the load current flowing through the string is measured. The peak current (Ipp) of a panel in the string is determined. A current equal to the difference of the load current and the peak current (Ipp) is generated in a current source connected across the output terminals of the panel. The panel is thereby operated at its maximum power point (MPP). To determine the peak current (Ipp) of the panel, the magnitude of current flowing through the panel is iteratively changed and the corresponding power generated by the panel is computed. The change in the current through the panel and the measurement of the corresponding power are repeated until a maximum power is determined as being generated by the panel. The maximum power corresponds to the maximum power point (MPP) and the peak current (Ipp) of the panel.

Abstract translation: 在包括一系列串联连接的面板的太阳能电池板阵列中，测量流过该串的负载电流。 确定字符串中面板的峰值电流（Ipp）。 在连接在面板的输出端子上的电流源中产生等于负载电流和峰值电流（Ipp）差的电流。 因此，面板以其最大功率点（MPP）运行。 为了确定面板的峰值电流（Ipp），流过面板的电流的大小被迭代地改变，并且计算面板产生的对应的功率。 重复通过面板的电流的变化和对应的功率的测量，直到最大功率被确定为由面板产生。 最大功率对应于面板的最大功率点（MPP）和峰值电流（Ipp）。