公开(公告)号：US10157139B2

公开(公告)日：2018-12-18

申请号：US15268895

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner

IPC: G06F12/00 ,  G06F12/0888 ,  G06F12/0815 ,  G06F12/0808 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0811 ,  G06F12/0891

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing asynchronous cache maintenance operations on a computing device, including activating a first asynchronous cache maintenance operation, determining whether an active address of a memory access request to a cache is in a first range of addresses of the first active asynchronous cache maintenance operation, and queuing the first active asynchronous cache maintenance operation as the first asynchronous cache maintenance operation in a fixup queue in response to determining that the active address is in the first range of addresses.

公开(公告)号：US09665489B2

公开(公告)日：2017-05-30

申请号：US14619628

申请日：2015-02-11

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  George Patsilaras ,  Andrew Edmund Turner ,  Anwar Quinones Rohillah

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/084 ,  G06F12/0851 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.

公开(公告)号：US20160232091A1

公开(公告)日：2016-08-11

申请号：US14619628

申请日：2015-02-11

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  George Patsilaras ,  Andrew Edmund Turner ,  Anwar Quinones Rohillah

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0851 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.

Abstract translation: 方面包括用于实现选择可用的共享高速缓冲存储器作为受害者高速缓存的计算设备，系统和方法。 计算设备可以使用可用的共享高速缓冲存储器空间来识别远程共享高速缓冲存储器，以用作受害者高速缓存。 为了选择适当的可用共享高速缓冲存储器，计算设备可以检索与所标识的远程共享高速缓冲存储器相关联的识别的远程共享高速缓冲存储器的数据或与所标识的远程共享高速缓冲存储器有关的诸如性能速度， 尺寸。 使用所检索的数据，计算设备可以确定所识别的远程共享高速缓冲存储器以用作受害者高速缓存，并选择确定的远程共享高速缓冲存储器以用作受害者高速缓存。

公开(公告)号：US11016898B2

公开(公告)日：2021-05-25

申请号：US16543328

申请日：2019-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik ,  Wesley James Holland ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06F12/0868 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/121 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/1072

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

公开(公告)号：US10747671B1

公开(公告)日：2020-08-18

申请号：US16269440

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： Wesley James Holland ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  George Patsilaras ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06T1/60 ,  G06F12/0862 ,  G06F12/1009

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

公开(公告)号：US10261910B2

公开(公告)日：2019-04-16

申请号：US15077534

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/0802 ,  G06F12/0875 ,  G06F12/0886

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

公开(公告)号：US10248565B2

公开(公告)日：2019-04-02

申请号：US15268791

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F9/45 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0817 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0831

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a computing device, including receiving an I/O coherent write request, generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request from the I/O coherent write request, sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory, and sending the second hybrid I/O coherent write request without the I/O coherent write data of the I/O coherent write request to a coherency domain.

公开(公告)号：US20180081804A1

公开(公告)日：2018-03-22

申请号：US15268768

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/0808 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0877

CPC classification number: G06F12/0808 ,  G06F9/505 ,  G06F9/5083 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0877 ,  G06F12/12 ,  G06F12/128 ,  G06F2209/509 ,  G06F2212/1041 ,  G06F2212/621

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing on a computing device. Aspect methods may include offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode, detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator, and switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator.

公开(公告)号：US09858196B2

公开(公告)日：2018-01-02

申请号：US14462773

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Ali Iranli ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/0886 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0893 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory.

公开(公告)号：US09489305B2

公开(公告)日：2016-11-08

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： George Patsilaras ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Kris Tiri ,  Jeong-Ho Woo ,  Anwar Rohillah ,  Feng Wang ,  Moinul Khan ,  Subbarao Palacharla

IPC: G06F12/00 ,  G06F12/08 ,  G06F1/32 ,  G06F13/16 ,  G06F9/46

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。