公开(公告)号：US09607153B2

公开(公告)日：2017-03-28

申请号：US13801375

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Kris Tiri ,  Matthew Scott McGregor ,  Yucong Tao

IPC: G06F11/30 ,  G06F1/00 ,  H04L29/06 ,  G06F11/00 ,  G06F21/57 ,  G06F1/06 ,  G06F1/04 ,  G06F11/07 ,  G06F21/72 ,  G06F21/55 ,  G06F21/00 ,  G06F21/70 ,  G06F21/60 ,  G06F21/71

CPC classification number: G06F21/57 ,  G06F1/04 ,  G06F1/06 ,  G06F11/0721 ,  G06F11/076 ,  G06F21/00 ,  G06F21/55 ,  G06F21/602 ,  G06F21/70 ,  G06F21/71 ,  G06F21/725

Abstract: Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

公开(公告)号：US09489305B2

公开(公告)日：2016-11-08

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： George Patsilaras ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Kris Tiri ,  Jeong-Ho Woo ,  Anwar Rohillah ,  Feng Wang ,  Moinul Khan ,  Subbarao Palacharla

IPC: G06F12/00 ,  G06F12/08 ,  G06F1/32 ,  G06F13/16 ,  G06F9/46

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。

公开(公告)号：US20150234761A1

公开(公告)日：2015-08-20

申请号：US14706203

申请日：2015-05-07

Applicant: QUALCOMM Incorporated

Inventor： Cristian Duroiu ,  Jaya Prakash Subramaniam Ganasan ,  Vinod Chamarty ,  Mark Michael Schaffer ,  Joshua Hirsch Stubbs ,  Robert Nicholson Gibson ,  Kris Tiri ,  Moinul Khan ,  Bohuslav Rychlik ,  Serag GadelRab ,  Simon Booth

IPC: G06F13/37 ,  G06F13/16 ,  G06F13/18 ,  G06F13/42

CPC classification number: G06F13/37 ,  G06F13/1626 ,  G06F13/18 ,  G06F13/362 ,  G06F13/4256 ,  G06F2213/0038 ,  G06F2213/0062 ,  G06F2213/0064 ,  G06F2213/36 ,  Y02D10/14

Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Abstract translation: 公开了用于基于健康信息在通信总线上仲裁总线事务的设备，系统，方法和计算机可读介质。 主设备的健康信息可用于调整主设备总线事务的优先级，以满足主设备的服务质量要求。 在一个实施例中，总线互连被提供和配置为将总线事务从多个主设备中的任一个传送到耦合总线互连的从设备。 总线互连还被配置为将多个主设备中的每一个的健康信息映射到虚拟优先级空间中。 总线互连还被配置为将虚拟优先级空间转换为多个主设备中的每一个的物理优先级。 总线互连还被配置为基于多个主设备的物理优先级来仲裁多个主设备的总线事务。