公开(公告)号：US20210065772A1

公开(公告)日：2021-03-04

申请号：US16945303

申请日：2020-07-31

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

IPC: G11C11/4074 ,  G11C11/409

Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

公开(公告)号：US20200073561A1

公开(公告)日：2020-03-05

申请号：US16115845

申请日：2018-08-29

Applicant: QUALCOMM Incorporated

Inventor： Yanru LI ,  Dexter Tamio CHUN

IPC: G06F3/06

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of controlling a memory of a computing device by an adaptive memory controller. The method includes collecting usage data from the computing device over a first bin, wherein the first bin is associated with a first weight, wherein the first weight is indicative of one or more of a first partial array self-refresh (PASR) setting a first partial array auto refresh (PAAR) setting and a first deep power down (DPD) setting. The method further includes associating the collected data with a second weight, adapting the first bin based on the second weight, wherein the second weight is indicative of one or more of a second PASR, PAAR, and DPD setting. The method further includes controlling the memory during the next first bin based on the second weight.

公开(公告)号：US20190056990A1

公开(公告)日：2019-02-21

申请号：US15682533

申请日：2017-08-21

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Alain ARTIERI ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/068 ,  G06F11/10

Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

公开(公告)号：US20160320826A1

公开(公告)日：2016-11-03

申请号：US14700017

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ali TAHA ,  Dexter Tamio CHUN

IPC: G06F1/32 ,  G06F12/02 ,  G11C14/00 ,  G11C7/10 ,  G11C11/406

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/205 ,  G11C11/406 ,  G11C14/0009 ,  G11C14/0054 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

Abstract translation: 提供了用于存储器功率降低的方法和装置。 该设备基于DRAM的功耗与DRAM中的数据相关联以及处理器中存储在DRAM中的数据的使用，确定在处理器的空闲状态期间是否将数据存储到DRAM或NVRAM中 关于由处理器使用存储在NVRAM中的数据以及与数据相关联的与第一功率状态和第二功率状态相关联的电流相关联的占空比，由NVRAM产生的功率消耗。 NVRAM是除闪存之外的一种非易失性随机存取存储器。 基于确定是否将数据存储在DRAM或NVRAM中，处理器将数据存储到DRAM或NVRAM之一中。

公开(公告)号：US20160307645A1

公开(公告)日：2016-10-20

申请号：US14691570

申请日：2015-04-20

Applicant: Qualcomm Incorporated

Inventor： Jung Pill KIM ,  Dexter Tamio CHUN ,  Jungwon SUH ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Yanru LI ,  Mosaddiq SAIFUDDIN ,  Xiangyu DONG

IPC: G11C29/44 ,  G06F11/07 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1048 ,  G11C11/401 ,  G11C29/42 ,  G11C29/76

Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

Abstract translation: 具有冗余区域的存储器在正常模式下操作并且检测到错误。 选择选择在线修复过程和离线修复。 在线修复应用短期错误纠正，其将失败地址重映射到存储器的重映射存储区域。 应用系统内修复，将故障地址的一次性重新映射重新映射到存储器的冗余区域。 系统内修复利用存储器的空闲时间来维护有效的存储器内容。

公开(公告)号：US20160291634A1

公开(公告)日：2016-10-06

申请号：US14677752

申请日：2015-04-02

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  David Ian WEST ,  Dexter Tamio CHUN

IPC: G06F1/14

CPC classification number: G06F1/3253 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/151

Abstract: A clock is distributed to a processor-side base mode clocked transceiver and to a memory-side base mode clocked transceiver, interfacing respective ends of a data lane between a processor and the memory, for duplex communicating over the data lane. Concurrent with the duplex communicating, a bandwidth mode switches between a base bandwidth mode and a scale-up mode. The scale-up mode enables scale-up clock lines that distribute the clock to a processor-side scale-up transceiver and to a memory-side scale-up transceiver, interfacing respective ends of a scale-up data lane between the processor and the memory, for additional duplex communicating over the scale-up data lane. The base bandwidth mode disables the scale-up clock lines, which disables communicating over the scale-up data lane.

Abstract translation: 时钟被分配到处理器侧基本模式时钟收发器和存储器侧基本模式时钟收发器，将处理器和存储器之间的数据通道的相应端接口连接，以在数据通道上进行双向通信。 与双工通信同时，带宽模式在基带宽模式和放大模式之间切换。 放大模式可实现将时钟分配给处理器侧放大收发器和存储器侧放大收发器的放大时钟线，将处理器与处理器之间的放大数据通道的各个端点相连接 存储器，用于通过放大数据通道进行额外的双工通信。 基带宽模式禁用放大时钟线，禁止通过放大数据通道进行通信。

公开(公告)号：US20160112183A1

公开(公告)日：2016-04-21

申请号：US14518587

申请日：2014-10-20

Applicant: QUALCOMM Incorporated

Inventor： Michael DROP ,  Dexter Tamio CHUN

IPC: H04L7/00 ,  H04L7/033

CPC classification number: G11C29/023 ,  G06F13/1689 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/1093 ,  G11C11/4076 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0008 ,  H04L7/0332

Abstract: Method and apparatus for signal sampling timing drift compensation are provided. Raw time values or deviations between clock and data are measured and filtered to generate filtered time information, and the filtered time information is compared to an upper bound and a lower bound. If the filtered time information is outside the upper and lower bounds, then an amount of timing compensation for the clock is computed. A signal is sent to reset the clock based on the amount of timing compensation.

Abstract translation: 提供了信号采样定时漂移补偿的方法和装置。 测量和滤波时间和时钟之间的时间值或时间差，以生成滤波时间信息，并将滤波的时间信息与上限和下限进行比较。 如果滤波时间信息在上限和下限之外，则计算时钟的定时补偿量。 根据定时补偿量发送一个信号来复位时钟。

公开(公告)号：US20220222137A1

公开(公告)日：2022-07-14

申请号：US17147110

申请日：2021-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru LI ,  Dexter Tamio CHUN

IPC: G06F11/10 ,  G06F16/907

Abstract: Transferring data between memories may include reading data associated with a memory transfer transaction from a first memory, determining whether a bypass indication associated with the memory transfer transaction is asserted, and transferring the data from the first memory to a second memory. The transferring may include bypassing the first-processing if the bypass indication is asserted. The transferring may further include bypassing second-processing the data if the bypass indication is asserted. Following bypassing the second-processing, the data may be stored in the second memory.

公开(公告)号：US20220027067A1

公开(公告)日：2022-01-27

申请号：US17494089

申请日：2021-10-05

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Dexter Tamio CHUN ,  Michael Hawjing LO ,  Shyamkumar THOZIYOOR ,  Ravindra KUMAR

IPC: G06F3/06 ,  G06F12/0875

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

公开(公告)号：US20210343331A1

公开(公告)日：2021-11-04

申请号：US17377799

申请日：2021-07-16

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Yanru LI ,  Michael Hawjing LO ,  Dexter Tamio CHUN

IPC: G11C11/406 ,  G11C7/10

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.