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    METHOD AND APPARATUS FOR DRAM SPATIAL COALESCING WITHIN A SINGLE CHANNEL
    12.
    发明申请
    METHOD AND APPARATUS FOR DRAM SPATIAL COALESCING WITHIN A SINGLE CHANNEL 有权
    用于单个通道中的DRAM空间分析的方法和装置

    公开(公告)号：US20150186267A1

    公开(公告)日：2015-07-02

    申请号：US14142573

    申请日：2013-12-27

    Applicant: QUALCOMM Incorporated

    Inventor： Dexter Tamio Chun ,  Haw-Jing Lo ,  Michael Drop

    IPC: G06F12/06

    CPC classification number: G06F12/06 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1673 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

    Abstract translation: 方面包括用于重新组织存储器中的数据存储器的计算设备，系统和方法，以激励小于用于读取或写入事务的存储器模块的所有存储器设备。 存储器件可以连接到单独的选择线，使得重新排序逻辑可以根据重新排序的存储器映射来确定存储器件激活事务。 重新排序逻辑可以重新排序存储器地址，使得由处理器为交易提供的存储器地址根据重新排序的存储器映射被转换为重新排序的存储器地址，而处理器不必改变其存储器地址方案。 重新排序的存储器映射可以提供由存储器件减少的能量消耗，或等待容忍过程的能量消耗和性能速度的平衡。

    Optimized error-correcting code (ECC) for data protection
    14.
    发明授权
    Optimized error-correcting code (ECC) for data protection 有权

    公开(公告)号：US11281526B2

    公开(公告)日：2022-03-22

    申请号：US17008442

    申请日：2020-08-31

    Applicant: QUALCOMM Incorporated

    Inventor： Alain Artieri ,  Deepti Vijayalakshmi Sriramagiri ,  Dexter Tamio Chun ,  Jungwon Suh

    IPC: G06F11/10 ,  G06F3/06 ,  H04L1/00 ,  H03M13/19 ,  G11C29/52 ,  G11C29/02 ,  G11C29/04

    Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.

    Dynamic link error protection in memory systems
    15.
    发明授权
    Dynamic link error protection in memory systems 有权

    公开(公告)号：US10922168B2

    公开(公告)日：2021-02-16

    申请号：US16503368

    申请日：2019-07-03

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon Suh ,  Alain Artieri ,  Dexter Tamio Chun ,  Deepti Vijayalakshmi Sriramagiri

    IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

    Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

    ENHANCED DATA CLOCK OPERATIONS IN MEMORY
    16.
    发明申请
    ENHANCED DATA CLOCK OPERATIONS IN MEMORY 审中-公开

    公开(公告)号：US20200278802A1

    公开(公告)日：2020-09-03

    申请号：US16803977

    申请日：2020-02-27

    Applicant: Qualcomm Incorporated

    Inventor： Jungwon SUH ,  Dexter Tamio Chun ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor ,  Ravindra Kumar

    IPC: G06F3/06 ,  G06F12/0875

    Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

    System memory latency compensation
    17.
    发明授权
    System memory latency compensation 有权

    公开(公告)号：US10359803B2

    公开(公告)日：2019-07-23

    申请号：US15601924

    申请日：2017-05-22

    Applicant: QUALCOMM INCORPORATED

    Inventor： Dexter Tamio Chun ,  Richard Alan Stewart

    IPC: G06F1/32 ,  G06F1/08 ,  G06F3/06 ,  G06F1/3234 ,  G06F1/324 ,  G06F13/16

    Abstract: Pipelined logic latency in a memory system operating at a reduced frequency may be compensated for. Pipelined logic may be controlled using at least first and second clock signals. All registers of the pipelined logic may be controlled using the first clock signal when the memory system is operating at a higher frequency. However, when the memory system is operating at a reduced frequency, one or more registers may be controlled using the first clock signal, and one or more other registers may be controlled using the second clock signal.

    Partial refresh technique to save memory refresh power
    18.
    发明授权
    Partial refresh technique to save memory refresh power 有权

    公开(公告)号：US10332582B2

    公开(公告)日：2019-06-25

    申请号：US15667618

    申请日：2017-08-02

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

    IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

    Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

    Unified memory controller for heterogeneous memory on a multi-chip package
    20.
    发明授权
    Unified memory controller for heterogeneous memory on a multi-chip package 有权

    公开(公告)号：US10185515B2

    公开(公告)日：2019-01-22

    申请号：US14016717

    申请日：2013-09-03

    Applicant: QUALCOMM Incorporated

    Inventor： Hyunsuk Shin ,  Jung Pill Kim ,  Dexter Tamio Chun ,  Jungwon Suh

    IPC: G06F3/06 ,  G06F13/16

    Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

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