公开(公告)号：US20180329830A1

公开(公告)日：2018-11-15

申请号：US15592611

申请日：2017-05-11

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/1045 ,  G06F3/06

CPC classification number: G06F12/1036 ,  G06F3/06 ,  G06F3/0608 ,  G06F3/0661 ,  G06F3/0685 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/60

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

公开(公告)号：US20170269851A1

公开(公告)日：2017-09-21

申请号：US15074444

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Amin Ansari ,  Richard Senior ,  Nieyan Geng ,  Anand Janakiraman ,  Gurvinder Singh Chhabra

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0611 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0615 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/401 ,  G06F2212/65

Abstract: Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.

公开(公告)号：US09600420B2

公开(公告)日：2017-03-21

申请号：US14526868

申请日：2014-10-29

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Richard Senior ,  Raghuveer Raghavendra ,  Nieyan Geng ,  Gurvinder Singh Chhabra

IPC: G06F12/00 ,  G06F12/12 ,  G06F12/10 ,  H03M7/30 ,  G06F12/08

CPC classification number: G06F12/12 ,  G06F12/08 ,  G06F12/1009 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/6017 ,  H03M7/6023 ,  H03M7/702

Abstract: Aspects include computing devices, systems, and methods for implementing executing decompression of a compressed page. A computing device may determine a decompression block of a compressed page that contains a code instruction requested in a memory access request. Decompression blocks, other than the decompression block containing the requested code instruction, may be selected for decompression based on being situated between an end of the compressed page and the decompression block containing the requested code instruction. Decompression blocks not identified for decompression may be substituted for a fault or exception code. The computing device may decompress decompression blocks identified for decompression, starting at the end of the compressed page and terminating the decompression of the compressed page upon filling all blocks with decompressed blocks, faults, or exception code. The remaining decompression blocks of the compressed page may be decompressed after or concurrently with the execution of the requested code instruction.

公开(公告)号：US11829292B1

公开(公告)日：2023-11-28

申请号：US17572472

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris Geng ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Kan Wang

IPC: G06F12/084 ,  G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0811

Abstract: A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.

公开(公告)号：US11687461B1

公开(公告)日：2023-06-27

申请号：US17572472

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris Geng ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Kan Wang

IPC: G06F12/084 ,  G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0811

Abstract: A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.

公开(公告)号：US20200089616A1

公开(公告)日：2020-03-19

申请号：US16130069

申请日：2018-09-13

Applicant: QUALCOMM Incorporated

Inventor： Nieyan GENG ,  Gurvinder Singh Chhabra ,  Caoye Shen ,  Samir Thakkar ,  Chuguang He

IPC: G06F12/109 ,  G06F9/50 ,  G06F9/4401 ,  G06F12/02 ,  G06F9/455

Abstract: Various embodiments include methods and devices for implementing external paging and swapping for dynamic modules on a computing device. Embodiments may include assigning static virtual addresses to a base image and dynamic modules of a static image of firmware of the computing device from a virtual address space for the static image, decompose static image into the base image and the dynamic modules, load the base image to an execution memory during a boot time from first partition of a storage memory, reserve a swap pool in the execution memory during the boot time, and load a dynamic module of the dynamic modules to the swap pool from a second partition of storage memory during a run time.

公开(公告)号：US10372459B2

公开(公告)日：2019-08-06

申请号：US15712112

申请日：2017-09-21

Applicant: QUALCOMM Incorporated

Inventor： Gurkanwal Brar ,  Christopher Ahn ,  Gurvinder Singh Chhabra

IPC: G06F9/38

Abstract: Systems and methods for branch prediction include identifying a subset of branch instructions from an execution trace of instructions executed by a processor. The identified subset of branch instructions have greater benefit from branch predictions made by a neural branch predictor than branch predictions made by a non-neural branch predictor. During runtime, the neural branch predictor is selectively used for obtaining branch predictions of the identified subset of branch instructions. For remaining branch instructions outside the identified subset of branch instructions, branch predictions are obtained from a non-neural branch predictor. Further, a weight vector matrix comprising weight vectors for the identified subset of branch instructions of the neural branch predictor is pre-trained based on the execution trace.

公开(公告)号：US10198362B2

公开(公告)日：2019-02-05

申请号：US15426473

申请日：2017-02-07

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/08 ,  G06F12/128 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/0897

Abstract: Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.

公开(公告)号：US09823854B2

公开(公告)日：2017-11-21

申请号：US15074444

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Amin Ansari ,  Richard Senior ,  Nieyan Geng ,  Anand Janakiraman ,  Gurvinder Singh Chhabra

IPC: G06F3/06 ,  G06F12/0897

CPC classification number: G06F3/0611 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0615 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/401 ,  G06F2212/65

Abstract: Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.

公开(公告)号：US09379887B2

公开(公告)日：2016-06-28

申请号：US14024424

申请日：2013-09-11

Applicant: QUALCOMM Incorporated

Inventor： Justin Y. Wei ,  Antoine Dambre ,  Christopher Ahn ,  Gurvinder Singh Chhabra

IPC: H04L9/08 ,  H04L9/06

CPC classification number: H04L9/0816 ,  H04L9/0662 ,  H04L9/0668 ,  H04L2209/12 ,  H04L2209/122

Abstract: Application of a ZUC cryptographic functions in wireless communication includes receiving a data stream at the wireless communication apparatus and applying the ZUC cryptographic function to the data stream. The ZUC cryptographic function includes generating at least one multi-byte pseudo-random number that provides an index to one of a plurality of substitution boxes. Each of the substitution boxes is further based on one or more normative substitution boxes. The ZUC cryptographic function further includes retrieving a value from each of the substitution boxes using each byte of the multi-byte pseudo-random number, assembling the retrieved values into at least one substituted values, and generating at least one key value based on the substituted values, wherein the key value is used in applying the ZUC cryptographic function to the data stream. The method also includes processing the data stream after application of the ZUC cryptographic function.

Abstract translation: ZUC加密功能在无线通信中的应用包括在无线通信装置处接收数据流并将ZUC加密功能应用于数据流。 ZUC加密功能包括生成至少一个多字节伪随机数，其向多个取代框之一提供索引。 每个替代框进一步基于一个或多个规范性替代框。 ZUC加密功能还包括使用多字节伪随机数的每个字节从每个替换盒中检索一个值，将检索到的值组装成至少一个替换值，并且基于取代的值生成至少一个密钥值 值，其中所述键值用于将ZUC加密功能应用于所述数据流。 该方法还包括在应用ZUC加密功能之后处理数据流。